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Add support for FP_ROUND from v2f64 to v2f32
- Due to the current matching vector elements constraints in ISD::FP_ROUND, rounding from v2f64 to v4f32 (after legalization from v2f32) is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPROUND to work around this constraints. llvm-svn: 165631
This commit is contained in:
Michael Liao
parent
c434bfd7e4
commit
6a09ff62ba
@ -940,6 +940,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
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setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
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setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
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setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
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}
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@ -11468,6 +11469,11 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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}
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return;
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}
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case ISD::FP_ROUND: {
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SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
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Results.push_back(V);
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return;
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}
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case ISD::READCYCLECOUNTER: {
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue TheChain = N->getOperand(0);
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@ -11662,6 +11668,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
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case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
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case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
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case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
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case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
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case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
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case X86ISD::VSHL: return "X86ISD::VSHL";
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@ -233,6 +233,9 @@ namespace llvm {
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// VFPEXT - Vector FP extend.
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VFPEXT,
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// VFPROUND - Vector FP round.
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VFPROUND,
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// VSHL, VSRL - 128-bit vector logical left / right shift
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VSHLDQ, VSRLDQ,
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@ -93,6 +93,9 @@ def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
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def X86vfpext : SDNode<"X86ISD::VFPEXT",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisFP<0>, SDTCisFP<1>]>>;
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def X86vfpround: SDNode<"X86ISD::VFPROUND",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisFP<0>, SDTCisFP<1>]>>;
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def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
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def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
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@ -2125,6 +2125,10 @@ let Predicates = [HasAVX] in {
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(VCVTDQ2PSYrm addr:$src)>;
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// Match fround and fextend for 128/256-bit conversions
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def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
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(VCVTPD2PSrr VR128:$src)>;
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def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
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(VCVTPD2PSXrm addr:$src)>;
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def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
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(VCVTPD2PSYrr VR256:$src)>;
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def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
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@ -2139,7 +2143,12 @@ let Predicates = [HasAVX] in {
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}
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let Predicates = [UseSSE2] in {
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// Match fextend for 128 conversions
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// Match fround and fextend for 128 conversions
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def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
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(CVTPD2PSrr VR128:$src)>;
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def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
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(CVTPD2PSrm addr:$src)>;
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def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
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(CVTPS2PDrr VR128:$src)>;
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}
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61
test/CodeGen/X86/fp-load-trunc.ll
Normal file
61
test/CodeGen/X86/fp-load-trunc.ll
Normal file
@ -0,0 +1,61 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2,-avx | FileCheck %s
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; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s --check-prefix=AVX
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define <1 x float> @test1(<1 x double>* %p) nounwind {
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; CHECK: test1
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; CHECK: cvtsd2ss
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; CHECK: ret
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; AVX: test1
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; AVX: vcvtsd2ss
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; AVX: ret
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%x = load <1 x double>* %p
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%y = fptrunc <1 x double> %x to <1 x float>
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ret <1 x float> %y
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}
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define <2 x float> @test2(<2 x double>* %p) nounwind {
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; CHECK: test2
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; CHECK: cvtpd2ps {{[0-9]*}}(%{{.*}})
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; CHECK: ret
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; AVX: test2
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; AVX: vcvtpd2psx {{[0-9]*}}(%{{.*}})
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; AVX: ret
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%x = load <2 x double>* %p
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%y = fptrunc <2 x double> %x to <2 x float>
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ret <2 x float> %y
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}
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define <4 x float> @test3(<4 x double>* %p) nounwind {
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; CHECK: test3
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; CHECK: cvtpd2ps {{[0-9]*}}(%{{.*}})
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; CHECK: cvtpd2ps {{[0-9]*}}(%{{.*}})
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; CHECK: movlhps
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; CHECK: ret
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; AVX: test3
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; AVX: vcvtpd2psy {{[0-9]*}}(%{{.*}})
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; AVX: ret
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%x = load <4 x double>* %p
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%y = fptrunc <4 x double> %x to <4 x float>
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ret <4 x float> %y
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}
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define <8 x float> @test4(<8 x double>* %p) nounwind {
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; CHECK: test4
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; CHECK: cvtpd2ps {{[0-9]*}}(%{{.*}})
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; CHECK: cvtpd2ps {{[0-9]*}}(%{{.*}})
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; CHECK: movlhps
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; CHECK: cvtpd2ps {{[0-9]*}}(%{{.*}})
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; CHECK: cvtpd2ps {{[0-9]*}}(%{{.*}})
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; CHECK: movlhps
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; CHECK: ret
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; AVX: test4
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; AVX: vcvtpd2psy {{[0-9]*}}(%{{.*}})
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; AVX: vcvtpd2psy {{[0-9]*}}(%{{.*}})
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; AVX: vinsertf128
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; AVX: ret
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%x = load <8 x double>* %p
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%y = fptrunc <8 x double> %x to <8 x float>
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ret <8 x float> %y
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}
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@ -1,33 +1,56 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2,-avx | FileCheck %s
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; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s --check-prefix=AVX
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define <1 x float> @test1(<1 x double> %x) nounwind {
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; CHECK: test1
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; CHECK: cvtsd2ss
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; CHECK: ret
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; AVX: test1
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; AVX: vcvtsd2ss
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; AVX: ret
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%y = fptrunc <1 x double> %x to <1 x float>
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ret <1 x float> %y
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}
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define <2 x float> @test2(<2 x double> %x) nounwind {
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; FIXME: It would be nice if this compiled down to a cvtpd2ps
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; CHECK: cvtsd2ss
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; CHECK: cvtsd2ss
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; CHECK: test2
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; CHECK: cvtpd2ps
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; CHECK: ret
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; AVX: test2
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; AVX-NOT: vcvtpd2psy
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; AVX: vcvtpd2ps
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; AVX: ret
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%y = fptrunc <2 x double> %x to <2 x float>
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ret <2 x float> %y
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}
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define <8 x float> @test3(<8 x double> %x) nounwind {
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; FIXME: It would be nice if this compiled down to a series of cvtpd2ps
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; CHECK: cvtsd2ss
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; CHECK: cvtsd2ss
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; CHECK: cvtsd2ss
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; CHECK: cvtsd2ss
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; CHECK: cvtsd2ss
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; CHECK: cvtsd2ss
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; CHECK: cvtsd2ss
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; CHECK: cvtsd2ss
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define <4 x float> @test3(<4 x double> %x) nounwind {
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; CHECK: test3
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; CHECK: cvtpd2ps
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; CHECK: cvtpd2ps
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; CHECK: movlhps
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; CHECK: ret
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; AVX: test3
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; AVX: vcvtpd2psy
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; AVX: ret
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%y = fptrunc <4 x double> %x to <4 x float>
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ret <4 x float> %y
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}
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define <8 x float> @test4(<8 x double> %x) nounwind {
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; CHECK: test4
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; CHECK: cvtpd2ps
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; CHECK: cvtpd2ps
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; CHECK: movlhps
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; CHECK: cvtpd2ps
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; CHECK: cvtpd2ps
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; CHECK: movlhps
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; CHECK: ret
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; AVX: test4
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; AVX: vcvtpd2psy
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; AVX: vcvtpd2psy
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; AVX: vinsertf128
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; AVX: ret
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%y = fptrunc <8 x double> %x to <8 x float>
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ret <8 x float> %y
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}
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