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Make code layout more consistent.
llvm-svn: 9418
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59ee30fa40
commit
6a1c1640f5
@ -1541,22 +1541,19 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// Let's check for chain rules outside the switch so that we don't have
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// Let's check for chain rules outside the switch so that we don't have
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// to duplicate the list of chain rule production numbers here again
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// to duplicate the list of chain rule production numbers here again
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//
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//
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if (ThisIsAChainRule(ruleForNode))
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if (ThisIsAChainRule(ruleForNode)) {
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{
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// Chain rules have a single nonterminal on the RHS.
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// Chain rules have a single nonterminal on the RHS.
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// Get the rule that matches the RHS non-terminal and use that instead.
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// Get the rule that matches the RHS non-terminal and use that instead.
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//
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//
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assert(nts[0] && ! nts[1]
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assert(nts[0] && ! nts[1]
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&& "A chain rule should have only one RHS non-terminal!");
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&& "A chain rule should have only one RHS non-terminal!");
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nextRule = burm_rule(subtreeRoot->state, nts[0]);
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nextRule = burm_rule(subtreeRoot->state, nts[0]);
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nts = burm_nts[nextRule];
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nts = burm_nts[nextRule];
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GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
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GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
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} else {
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}
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switch(ruleForNode) {
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else
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case 1: // stmt: Ret
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{
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case 2: // stmt: RetValue(reg)
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switch(ruleForNode) {
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case 1: // stmt: Ret
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case 2: // stmt: RetValue(reg)
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{ // NOTE: Prepass of register allocation is responsible
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{ // NOTE: Prepass of register allocation is responsible
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// for moving return value to appropriate register.
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// for moving return value to appropriate register.
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// Copy the return value to the required return register.
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// Copy the return value to the required return register.
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@ -2192,11 +2189,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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mvec.push_back(BuildMI(V9::ANDNr, 3).addReg(lhs).addReg(notArg)
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mvec.push_back(BuildMI(V9::ANDNr, 3).addReg(lhs).addReg(notArg)
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.addReg(dest, MOTy::Def));
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.addReg(dest, MOTy::Def));
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if (notArg->getType() == Type::BoolTy)
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if (notArg->getType() == Type::BoolTy) {
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{ // set 1 in result register if result of above is non-zero
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// set 1 in result register if result of above is non-zero
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mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
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mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
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.addReg(dest, MOTy::UseAndDef));
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.addReg(dest, MOTy::UseAndDef));
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}
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}
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break;
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break;
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}
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}
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@ -2223,11 +2220,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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mvec.push_back(BuildMI(V9::ORNr, 3).addReg(lhs).addReg(notArg)
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mvec.push_back(BuildMI(V9::ORNr, 3).addReg(lhs).addReg(notArg)
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.addReg(dest, MOTy::Def));
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.addReg(dest, MOTy::Def));
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if (notArg->getType() == Type::BoolTy)
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if (notArg->getType() == Type::BoolTy) {
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{ // set 1 in result register if result of above is non-zero
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// set 1 in result register if result of above is non-zero
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mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
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mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
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.addReg(dest, MOTy::UseAndDef));
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.addReg(dest, MOTy::UseAndDef));
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}
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}
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break;
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break;
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}
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}
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@ -2253,11 +2250,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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mvec.push_back(BuildMI(V9::XNORr, 3).addReg(lhs).addReg(notArg)
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mvec.push_back(BuildMI(V9::XNORr, 3).addReg(lhs).addReg(notArg)
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.addReg(dest, MOTy::Def));
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.addReg(dest, MOTy::Def));
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if (notArg->getType() == Type::BoolTy)
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if (notArg->getType() == Type::BoolTy) {
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{ // set 1 in result register if result of above is non-zero
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// set 1 in result register if result of above is non-zero
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mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
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mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
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.addReg(dest, MOTy::UseAndDef));
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.addReg(dest, MOTy::UseAndDef));
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}
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}
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break;
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break;
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}
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}
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@ -2278,37 +2275,36 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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bool computeBoolVal = (subtreeRoot->parent() == NULL ||
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bool computeBoolVal = (subtreeRoot->parent() == NULL ||
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! AllUsesAreBranches(setCCInstr));
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! AllUsesAreBranches(setCCInstr));
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if (computeBoolVal)
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if (computeBoolVal) {
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{
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InstrTreeNode* constNode = subtreeRoot->rightChild();
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InstrTreeNode* constNode = subtreeRoot->rightChild();
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assert(constNode &&
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assert(constNode &&
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constNode->getNodeType() ==InstrTreeNode::NTConstNode);
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constNode->getNodeType() ==InstrTreeNode::NTConstNode);
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Constant *constVal = cast<Constant>(constNode->getValue());
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Constant *constVal = cast<Constant>(constNode->getValue());
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bool isValidConst;
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bool isValidConst;
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if ((constVal->getType()->isInteger()
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if ((constVal->getType()->isInteger()
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|| isa<PointerType>(constVal->getType()))
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|| isa<PointerType>(constVal->getType()))
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&& target.getInstrInfo().ConvertConstantToIntType(target,
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&& target.getInstrInfo().ConvertConstantToIntType(target,
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constVal, constVal->getType(), isValidConst) == 0
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constVal, constVal->getType(), isValidConst) == 0
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&& isValidConst)
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&& isValidConst)
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{
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{
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// That constant is an integer zero after all...
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// That constant is an integer zero after all...
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// Use a MOVR[op] to compute the boolean result
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// Use a MOVR[op] to compute the boolean result
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// Unconditionally set register to 0
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// Unconditionally set register to 0
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mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0)
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mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0)
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.addRegDef(setCCInstr));
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.addRegDef(setCCInstr));
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// Now conditionally move 1 into the register.
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// Now conditionally move 1 into the register.
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// Mark the register as a use (as well as a def) because the old
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// Mark the register as a use (as well as a def) because the old
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// value will be retained if the condition is false.
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// value will be retained if the condition is false.
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MachineOpCode movOpCode = ChooseMovpregiForSetCC(subtreeRoot);
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MachineOpCode movOpCode = ChooseMovpregiForSetCC(subtreeRoot);
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mvec.push_back(BuildMI(movOpCode, 3)
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mvec.push_back(BuildMI(movOpCode, 3)
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.addReg(subtreeRoot->leftChild()->getValue())
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.addReg(subtreeRoot->leftChild()->getValue())
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.addZImm(1).addReg(setCCInstr, MOTy::UseAndDef));
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.addZImm(1).addReg(setCCInstr, MOTy::UseAndDef));
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break;
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break;
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}
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}
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}
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}
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// ELSE FALL THROUGH
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// ELSE FALL THROUGH
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}
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}
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