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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00

Make code layout more consistent.

llvm-svn: 9418
This commit is contained in:
Misha Brukman 2003-10-23 16:48:30 +00:00
parent 59ee30fa40
commit 6a1c1640f5

View File

@ -1541,22 +1541,19 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
// Let's check for chain rules outside the switch so that we don't have // Let's check for chain rules outside the switch so that we don't have
// to duplicate the list of chain rule production numbers here again // to duplicate the list of chain rule production numbers here again
// //
if (ThisIsAChainRule(ruleForNode)) if (ThisIsAChainRule(ruleForNode)) {
{ // Chain rules have a single nonterminal on the RHS.
// Chain rules have a single nonterminal on the RHS. // Get the rule that matches the RHS non-terminal and use that instead.
// Get the rule that matches the RHS non-terminal and use that instead. //
// assert(nts[0] && ! nts[1]
assert(nts[0] && ! nts[1] && "A chain rule should have only one RHS non-terminal!");
&& "A chain rule should have only one RHS non-terminal!"); nextRule = burm_rule(subtreeRoot->state, nts[0]);
nextRule = burm_rule(subtreeRoot->state, nts[0]); nts = burm_nts[nextRule];
nts = burm_nts[nextRule]; GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec); } else {
} switch(ruleForNode) {
else case 1: // stmt: Ret
{ case 2: // stmt: RetValue(reg)
switch(ruleForNode) {
case 1: // stmt: Ret
case 2: // stmt: RetValue(reg)
{ // NOTE: Prepass of register allocation is responsible { // NOTE: Prepass of register allocation is responsible
// for moving return value to appropriate register. // for moving return value to appropriate register.
// Copy the return value to the required return register. // Copy the return value to the required return register.
@ -2192,11 +2189,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
mvec.push_back(BuildMI(V9::ANDNr, 3).addReg(lhs).addReg(notArg) mvec.push_back(BuildMI(V9::ANDNr, 3).addReg(lhs).addReg(notArg)
.addReg(dest, MOTy::Def)); .addReg(dest, MOTy::Def));
if (notArg->getType() == Type::BoolTy) if (notArg->getType() == Type::BoolTy) {
{ // set 1 in result register if result of above is non-zero // set 1 in result register if result of above is non-zero
mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1) mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
.addReg(dest, MOTy::UseAndDef)); .addReg(dest, MOTy::UseAndDef));
} }
break; break;
} }
@ -2223,11 +2220,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
mvec.push_back(BuildMI(V9::ORNr, 3).addReg(lhs).addReg(notArg) mvec.push_back(BuildMI(V9::ORNr, 3).addReg(lhs).addReg(notArg)
.addReg(dest, MOTy::Def)); .addReg(dest, MOTy::Def));
if (notArg->getType() == Type::BoolTy) if (notArg->getType() == Type::BoolTy) {
{ // set 1 in result register if result of above is non-zero // set 1 in result register if result of above is non-zero
mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1) mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
.addReg(dest, MOTy::UseAndDef)); .addReg(dest, MOTy::UseAndDef));
} }
break; break;
} }
@ -2253,11 +2250,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
mvec.push_back(BuildMI(V9::XNORr, 3).addReg(lhs).addReg(notArg) mvec.push_back(BuildMI(V9::XNORr, 3).addReg(lhs).addReg(notArg)
.addReg(dest, MOTy::Def)); .addReg(dest, MOTy::Def));
if (notArg->getType() == Type::BoolTy) if (notArg->getType() == Type::BoolTy) {
{ // set 1 in result register if result of above is non-zero // set 1 in result register if result of above is non-zero
mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1) mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
.addReg(dest, MOTy::UseAndDef)); .addReg(dest, MOTy::UseAndDef));
} }
break; break;
} }
@ -2278,37 +2275,36 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
bool computeBoolVal = (subtreeRoot->parent() == NULL || bool computeBoolVal = (subtreeRoot->parent() == NULL ||
! AllUsesAreBranches(setCCInstr)); ! AllUsesAreBranches(setCCInstr));
if (computeBoolVal) if (computeBoolVal) {
{ InstrTreeNode* constNode = subtreeRoot->rightChild();
InstrTreeNode* constNode = subtreeRoot->rightChild(); assert(constNode &&
assert(constNode && constNode->getNodeType() ==InstrTreeNode::NTConstNode);
constNode->getNodeType() ==InstrTreeNode::NTConstNode); Constant *constVal = cast<Constant>(constNode->getValue());
Constant *constVal = cast<Constant>(constNode->getValue()); bool isValidConst;
bool isValidConst;
if ((constVal->getType()->isInteger()
if ((constVal->getType()->isInteger() || isa<PointerType>(constVal->getType()))
|| isa<PointerType>(constVal->getType())) && target.getInstrInfo().ConvertConstantToIntType(target,
&& target.getInstrInfo().ConvertConstantToIntType(target,
constVal, constVal->getType(), isValidConst) == 0 constVal, constVal->getType(), isValidConst) == 0
&& isValidConst) && isValidConst)
{ {
// That constant is an integer zero after all... // That constant is an integer zero after all...
// Use a MOVR[op] to compute the boolean result // Use a MOVR[op] to compute the boolean result
// Unconditionally set register to 0 // Unconditionally set register to 0
mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0) mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0)
.addRegDef(setCCInstr)); .addRegDef(setCCInstr));
// Now conditionally move 1 into the register. // Now conditionally move 1 into the register.
// Mark the register as a use (as well as a def) because the old // Mark the register as a use (as well as a def) because the old
// value will be retained if the condition is false. // value will be retained if the condition is false.
MachineOpCode movOpCode = ChooseMovpregiForSetCC(subtreeRoot); MachineOpCode movOpCode = ChooseMovpregiForSetCC(subtreeRoot);
mvec.push_back(BuildMI(movOpCode, 3) mvec.push_back(BuildMI(movOpCode, 3)
.addReg(subtreeRoot->leftChild()->getValue()) .addReg(subtreeRoot->leftChild()->getValue())
.addZImm(1).addReg(setCCInstr, MOTy::UseAndDef)); .addZImm(1).addReg(setCCInstr, MOTy::UseAndDef));
break; break;
}
} }
}
// ELSE FALL THROUGH // ELSE FALL THROUGH
} }