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[AArch64] Fix BTI instruction emission.

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Summary:
SCTLR_EL1.BT[01] controls the PACI[AB]SP compatibility with PBYTE 11
(see [1])
This bit will be set to zero so PACI[AB]SP are equal to BTI C
instruction only.

[1] https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/sctlr_el1

Reviewers: chill, tamas.petz, pbarrio, ostannard

Reviewed By: tamas.petz, ostannard

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81746
This commit is contained in:
Daniel Kiss 2020-06-15 15:02:38 +02:00
parent 192bd6b78c
commit 6a4188bf64
2 changed files with 15 additions and 5 deletions
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8
lib/Target/AArch64/AArch64BranchTargets.cpp
View File

@ -122,9 +122,11 @@ void AArch64BranchTargets::addBTI(MachineBasicBlock &MBB, bool CouldCall,
for (; MBBI != MBB.end() && MBBI->isMetaInstruction(); ++MBBI)
;
// PACI[AB]SP are implicitly BTI JC, so no BTI instruction needed there.
if (MBBI != MBB.end() && (MBBI->getOpcode() == AArch64::PACIASP ||
MBBI->getOpcode() == AArch64::PACIBSP))
// SCTLR_EL1.BT[01] is set to 0 by default which means
// PACI[AB]SP are implicitly BTI C so no BTI C instruction is needed there.
if (MBBI != MBB.end() && HintNum == 34 &&
(MBBI->getOpcode() == AArch64::PACIASP ||
MBBI->getOpcode() == AArch64::PACIBSP))
return;
BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),

12
test/CodeGen/AArch64/branch-target-enforcement.mir
View File

@ -292,6 +292,10 @@ body: |
---
# Function takes address of the entry block, so the entry block needs a BTI JC.
name: label_address_entry
stack:
- { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
bb.0.entry (address-taken):
; CHECK-LABEL: label_address_entry
@ -310,12 +314,16 @@ body: |
; CHECK: bb.1.return (address-taken):
; CHECK-NEXT: HINT 36
liveins: $x8
frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
frame-setup CFI_INSTRUCTION negate_ra_sign_state
early-clobber $sp = frame-setup STRXpre killed $lr, $sp, -16 :: (store 8 into %stack.0)
INLINEASM &"", 1, 12, implicit-def dead early-clobber $lr
$x9 = ADRP target-flags(aarch64-page) blockaddress(@label_address, %ir-block.entry)
renamable $w0 = ORRWri $wzr, 0
renamable $x9 = ADDXri killed $x9, target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@label_address, %ir-block.entry), 0
STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (store 8 into @label_address.addr)
RET undef $lr, implicit killed $w0
early-clobber $sp, $lr = frame-destroy LDRXpost $sp, 16 :: (load 8 from %stack.0)
RETAA implicit $sp, implicit $lr, implicit killed $w0
bb.2.lab2:
; CHECK: bb.2.lab2: