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[AArch64][GlobalISel] Add isel support for G_BLOCK_ADDR.
Also refactors some existing code to materialize addresses for the large code model so it can be shared between G_GLOBAL_VALUE and G_BLOCK_ADDR. This implements PR36390. Differential Revision: https://reviews.llvm.org/D49903 llvm-svn: 338337
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Amara Emerson
parent
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commit
6a47e74b23
@ -21,6 +21,7 @@
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -94,6 +95,10 @@ private:
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void renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI) const;
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// Materialize a GlobalValue or BlockAddress using a movz+movk sequence.
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void materializeLargeCMVal(MachineInstr &I, const Value *V,
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unsigned char OpFlags) const;
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const AArch64TargetMachine &TM;
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const AArch64Subtarget &STI;
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const AArch64InstrInfo &TII;
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@ -655,6 +660,45 @@ bool AArch64InstructionSelector::selectVaStartDarwin(
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return true;
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}
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void AArch64InstructionSelector::materializeLargeCMVal(
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MachineInstr &I, const Value *V, unsigned char OpFlags) const {
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineIRBuilder MIB(I);
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auto MovZ = MIB.buildInstr(AArch64::MOVZXi, &AArch64::GPR64RegClass);
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MovZ->addOperand(MF, I.getOperand(1));
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MovZ->getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_G0 |
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AArch64II::MO_NC);
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MovZ->addOperand(MF, MachineOperand::CreateImm(0));
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constrainSelectedInstRegOperands(*MovZ, TII, TRI, RBI);
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auto BuildMovK = [&](unsigned SrcReg, unsigned char Flags, unsigned Offset,
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unsigned ForceDstReg) {
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unsigned DstReg = ForceDstReg
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? ForceDstReg
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: MRI.createVirtualRegister(&AArch64::GPR64RegClass);
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auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg);
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if (auto *GV = dyn_cast<GlobalValue>(V)) {
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MovI->addOperand(MF, MachineOperand::CreateGA(
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GV, MovZ->getOperand(1).getOffset(), Flags));
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} else {
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MovI->addOperand(
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MF, MachineOperand::CreateBA(cast<BlockAddress>(V),
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MovZ->getOperand(1).getOffset(), Flags));
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}
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MovI->addOperand(MF, MachineOperand::CreateImm(Offset));
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constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI);
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return DstReg;
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};
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unsigned DstReg = BuildMovK(MovZ->getOperand(0).getReg(),
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AArch64II::MO_G1 | AArch64II::MO_NC, 16, 0);
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DstReg = BuildMovK(DstReg, AArch64II::MO_G2 | AArch64II::MO_NC, 32, 0);
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BuildMovK(DstReg, AArch64II::MO_G3, 48, I.getOperand(0).getReg());
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return;
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}
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bool AArch64InstructionSelector::select(MachineInstr &I,
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CodeGenCoverage &CoverageInfo) const {
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assert(I.getParent() && "Instruction should be in a basic block!");
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@ -936,36 +980,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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I.getOperand(1).setTargetFlags(OpFlags);
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} else if (TM.getCodeModel() == CodeModel::Large) {
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// Materialize the global using movz/movk instructions.
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unsigned MovZDstReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
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auto InsertPt = std::next(I.getIterator());
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auto MovZ =
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BuildMI(MBB, InsertPt, I.getDebugLoc(), TII.get(AArch64::MOVZXi))
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.addDef(MovZDstReg);
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MovZ->addOperand(MF, I.getOperand(1));
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MovZ->getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_G0 |
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AArch64II::MO_NC);
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MovZ->addOperand(MF, MachineOperand::CreateImm(0));
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constrainSelectedInstRegOperands(*MovZ, TII, TRI, RBI);
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auto BuildMovK = [&](unsigned SrcReg, unsigned char Flags,
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unsigned Offset, unsigned ForceDstReg) {
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unsigned DstReg =
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ForceDstReg ? ForceDstReg
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: MRI.createVirtualRegister(&AArch64::GPR64RegClass);
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auto MovI = BuildMI(MBB, InsertPt, MovZ->getDebugLoc(),
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TII.get(AArch64::MOVKXi))
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.addDef(DstReg)
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.addReg(SrcReg);
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MovI->addOperand(MF, MachineOperand::CreateGA(
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GV, MovZ->getOperand(1).getOffset(), Flags));
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MovI->addOperand(MF, MachineOperand::CreateImm(Offset));
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constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI);
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return DstReg;
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};
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unsigned DstReg = BuildMovK(MovZ->getOperand(0).getReg(),
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AArch64II::MO_G1 | AArch64II::MO_NC, 16, 0);
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DstReg = BuildMovK(DstReg, AArch64II::MO_G2 | AArch64II::MO_NC, 32, 0);
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BuildMovK(DstReg, AArch64II::MO_G3, 48, I.getOperand(0).getReg());
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materializeLargeCMVal(I, GV, OpFlags);
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I.eraseFromParent();
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return true;
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} else {
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@ -1482,7 +1497,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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.addImm(1);
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I.eraseFromParent();
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return true;
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case TargetOpcode::G_IMPLICIT_DEF:
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case TargetOpcode::G_IMPLICIT_DEF: {
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I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
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const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
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const unsigned DstReg = I.getOperand(0).getReg();
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@ -1492,6 +1507,25 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
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return true;
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}
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case TargetOpcode::G_BLOCK_ADDR: {
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if (TM.getCodeModel() == CodeModel::Large) {
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materializeLargeCMVal(I, I.getOperand(1).getBlockAddress(), 0);
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I.eraseFromParent();
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return true;
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} else {
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I.setDesc(TII.get(AArch64::MOVaddrBA));
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auto MovMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::MOVaddrBA),
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I.getOperand(0).getReg())
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.addBlockAddress(I.getOperand(1).getBlockAddress(),
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/* Offset */ 0, AArch64II::MO_PAGE)
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.addBlockAddress(
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I.getOperand(1).getBlockAddress(), /* Offset */ 0,
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AArch64II::MO_NC | AArch64II::MO_PAGEOFF);
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I.eraseFromParent();
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return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
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}
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}
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}
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return false;
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}
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64
test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
Normal file
64
test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
Normal file
@ -0,0 +1,64 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s
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# RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select -code-model=large %s | FileCheck %s --check-prefix=LARGE
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--- |
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; ModuleID = 'blockaddress.ll'
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source_filename = "blockaddress.ll"
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-none-linux-gnu"
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@addr = global i8* null
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define void @test_blockaddress() {
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store i8* blockaddress(@test_blockaddress, %block), i8** @addr
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indirectbr i8* blockaddress(@test_blockaddress, %block), [label %block]
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block: ; preds = %0
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ret void
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}
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...
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---
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name: test_blockaddress
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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; CHECK-LABEL: name: test_blockaddress
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; CHECK: bb.0 (%ir-block.0):
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[MOVaddrBA:%[0-9]+]]:gpr64 = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block)
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; CHECK: [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, aarch64-nc) @addr
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; CHECK: STRXui [[MOVaddrBA]], [[MOVaddr]], 0 :: (store 8 into @addr)
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; CHECK: BR [[MOVaddrBA]]
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; CHECK: bb.1.block (address-taken):
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; CHECK: RET_ReallyLR
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; LARGE-LABEL: name: test_blockaddress
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; LARGE: bb.0 (%ir-block.0):
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; LARGE: successors: %bb.1(0x80000000)
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; LARGE: [[MOVZXi:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 0
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; LARGE: [[MOVKXi:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi]], target-flags(aarch64-g1, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 16
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; LARGE: [[MOVKXi1:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi]], target-flags(aarch64-g2, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 32
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; LARGE: [[MOVKXi2:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi1]], target-flags(aarch64-g3) blockaddress(@test_blockaddress, %ir-block.block), 48
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; LARGE: [[MOVZXi1:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) @addr, 0
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; LARGE: [[MOVKXi3:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi1]], target-flags(aarch64-g1, aarch64-nc) @addr, 16
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; LARGE: [[MOVKXi4:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi3]], target-flags(aarch64-g2, aarch64-nc) @addr, 32
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; LARGE: [[MOVKXi5:%[0-9]+]]:gpr64common = MOVKXi [[MOVKXi4]], target-flags(aarch64-g3) @addr, 48
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; LARGE: STRXui [[MOVKXi2]], [[MOVKXi5]], 0 :: (store 8 into @addr)
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; LARGE: BR [[MOVKXi2]]
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; LARGE: bb.1.block (address-taken):
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; LARGE: RET_ReallyLR
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bb.1 (%ir-block.0):
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%0:gpr(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
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%1:gpr(p0) = G_GLOBAL_VALUE @addr
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G_STORE %0(p0), %1(p0) :: (store 8 into @addr)
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G_BRINDIRECT %0(p0)
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bb.2.block (address-taken):
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RET_ReallyLR
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...
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