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[AArch4][GlobalISel] Post-legalize combine s64 = G_MERGE s32, 0 -> G_ZEXT.
These are generated as a byproduce of legalization. Differential Revision: https://reviews.llvm.org/D106768
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@ -182,6 +182,13 @@ def form_truncstore : GICombineRule<
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(apply [{ applyFormTruncstore(*${root}, MRI, B, Observer, ${matchinfo}); }])
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>;
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def fold_merge_to_zext : GICombineRule<
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(defs root:$d),
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(match (wip_match_opcode G_MERGE_VALUES):$d,
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[{ return matchFoldMergeToZext(*${d}, MRI); }]),
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(apply [{ applyFoldMergeToZext(*${d}, MRI, B, Observer); }])
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>;
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// Post-legalization combines which should happen at all optimization levels.
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// (E.g. ones that facilitate matching for the selector) For example, matching
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// pseudos.
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@ -204,6 +211,6 @@ def AArch64PostLegalizerCombinerHelper
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mul_const, redundant_sext_inreg,
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form_bitfield_extract, rotate_out_of_range,
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icmp_to_true_false_known_bits, merge_unmerge,
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select_combines]> {
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select_combines, fold_merge_to_zext]> {
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let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
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}
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@ -23,6 +23,7 @@
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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@ -240,6 +241,27 @@ bool applyAArch64MulConstCombine(
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return true;
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}
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/// Try to fold a G_MERGE_VALUES of 2 s32 sources, where the second source
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/// is a zero, into a G_ZEXT of the first.
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bool matchFoldMergeToZext(MachineInstr &MI, MachineRegisterInfo &MRI) {
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auto &Merge = cast<GMerge>(MI);
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LLT SrcTy = MRI.getType(Merge.getSourceReg(0));
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if (SrcTy != LLT::scalar(32) || Merge.getNumSources() != 2)
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return false;
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return mi_match(Merge.getSourceReg(1), MRI, m_SpecificICst(0));
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}
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void applyFoldMergeToZext(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, GISelChangeObserver &Observer) {
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// Mutate %d(s64) = G_MERGE_VALUES %a(s32), 0(s32)
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// ->
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// %d(s64) = G_ZEXT %a(s32)
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Observer.changingInstr(MI);
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MI.setDesc(B.getTII().get(TargetOpcode::G_ZEXT));
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MI.RemoveOperand(2);
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Observer.changedInstr(MI);
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}
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#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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#include "AArch64GenPostLegalizeGICombiner.inc"
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#undef AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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@ -68,3 +68,25 @@ body: |
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RET_ReallyLR implicit $x0
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...
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---
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name: merge_to_zext
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alignment: 4
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legalized: true
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liveins:
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- { reg: '$w0' }
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body: |
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bb.1.entry:
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liveins: $w0
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; CHECK-LABEL: name: merge_to_zext
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; CHECK: %v:_(s32) = COPY $w0
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; CHECK: %merge:_(s64) = G_ZEXT %v(s32)
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; CHECK: $x0 = COPY %merge(s64)
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; CHECK: RET_ReallyLR implicit $x0
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%v:_(s32) = COPY $w0
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%zero:_(s32) = G_CONSTANT i32 0
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%merge:_(s64) = G_MERGE_VALUES %v, %zero
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$x0 = COPY %merge(s64)
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RET_ReallyLR implicit $x0
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...
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