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AMDGPU/GlobalISel: Mark 1-bit integer constants as legal

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Summary:
These are mostly legal, but will probably need special lowering for some
cases.

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D33791

llvm-svn: 304628
This commit is contained in:
Tom Stellard 2017-06-03 01:13:33 +00:00
parent df0fc08844
commit 6a773e4535
2 changed files with 14 additions and 0 deletions
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5
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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@ -28,11 +28,16 @@ using namespace llvm;
AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
using namespace TargetOpcode;
const LLT S1= LLT::scalar(1);
const LLT S32 = LLT::scalar(32);
const LLT S64 = LLT::scalar(64);
const LLT P1 = LLT::pointer(1, 64);
const LLT P2 = LLT::pointer(2, 64);
// FIXME: i1 operands to intrinsics should always be legal, but other i1
// values may not be legal. We need to figure out how to distinguish
// between these two scenarios.
setAction({G_CONSTANT, S1}, Legal);
setAction({G_CONSTANT, S32}, Legal);
setAction({G_CONSTANT, S64}, Legal);

9
test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
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@ -10,18 +10,27 @@
entry:
ret void
}
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
attributes #1 = { nounwind }
...
---
name: test_constant
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0.entry:
; CHECK-LABEL: name: test_constant
; CHECK: %0(s32) = G_CONSTANT i32 5
; CHECK: %1(s1) = G_CONSTANT i1 false
%0(s32) = G_CONSTANT i32 5
%1(s1) = G_CONSTANT i1 0
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), %0, %0, %0, %0, %0, %0, %1, %1;
...
---