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PPC: Don't select lxv/stxv for insufficiently aligned stack slots.

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The lxv/stxv instructions require an offset that is 0 % 16. Previously we were
selecting lxv/stxv for loads and stores to the stack where the offset from the
slot was a multiple of 16, but the stack slot was not 16 or more byte aligned.
When the frame gets lowered these transform to r(1|31) + slot + offset.
If slot is not aligned, slot + offset may not be 0 % 16.
Now we require 16 byte or more alignment for select lxv/stxv to stack slots.

Includes a testcase that shows both sufficiently and insufficiently aligned
stack slots.

llvm-svn: 312843
This commit is contained in:
Kyle Butt 2017-09-09 00:37:56 +00:00
parent a47d225a61
commit 6ab29ccb20
2 changed files with 57 additions and 1 deletions
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12
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -3055,8 +3055,18 @@ bool PPCDAGToDAGISel::isOffsetMultipleOf(SDNode *N, unsigned Val) const {
AddrOp = STN->getOperand(2);
short Imm = 0;
if (AddrOp.getOpcode() == ISD::ADD)
if (AddrOp.getOpcode() == ISD::ADD) {
// If op0 is a frame index that is under aligned, we can't do it either,
// because it is translated to r31 or r1 + slot + offset. We won't know the
// slot number until the stack frame is finalized.
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddrOp.getOperand(0))) {
const MachineFrameInfo &MFI = CurDAG->getMachineFunction().getFrameInfo();
unsigned SlotAlign = MFI.getObjectAlignment(FI->getIndex());
if ((SlotAlign % Val) != 0)
return false;
}
return isIntS16Immediate(AddrOp.getOperand(1), Imm) && !(Imm % Val);
}
// If the address comes from the outside, the offset will be zero.
return AddrOp.getOpcode() == ISD::CopyFromReg;

46
test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll Normal file
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@ -0,0 +1,46 @@
; RUN: llc -O3 -o - %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
%class1 = type { %union1 }
%union1 = type { i64, [24 x i8] }
%class2 = type { %class3 }
%class3 = type { %class4 }
%class4 = type { %class5, i64, %union.anon }
%class5 = type { i8* }
%union.anon = type { i64, [8 x i8] }
@ext = external global %"class1", align 8
; We can't select lxv for this because even though we're accessing an offset of
; 16 from the stack slot, the stack slot is only guaranteed to be 8-byte
; aligned. When the frame is finalized it is converted to lxv (frame-reg) +
; (offset + 16). Because offset isn't guaranteed to be 16-byte aligned, we may
; end up needing to translate the lxv instruction to lxvx
; CHECK-LABEL: unaligned_slot:
; CHECK-NOT: lxv {{[0-9]+}}, {{[-0-9]+}}({{[0-9]+}})
; CHECK: blr
define void @unaligned_slot() #0 {
%1 = alloca %class2, align 8
%2 = getelementptr inbounds %class2, %class2* %1, i64 0, i32 0, i32 0, i32 2
%3 = bitcast %union.anon* %2 to i8*
call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull getelementptr inbounds (%class1, %class1* @ext, i64 0, i32 0, i32 1, i64 8), i8* nonnull %3, i64 16, i32 8, i1 false) #2
ret void
}
; CHECK-LABEL: aligned_slot:
; CHECK: lxv {{[0-9]+}}, {{[-0-9]+}}({{[0-9]+}})
; CHECK: blr
define void @aligned_slot() #0 {
%1 = alloca %class2, align 16
%2 = getelementptr inbounds %class2, %class2* %1, i64 0, i32 0, i32 0, i32 2
%3 = bitcast %union.anon* %2 to i8*
call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull getelementptr inbounds (%class1, %class1* @ext, i64 0, i32 0, i32 1, i64 8), i8* nonnull %3, i64 16, i32 8, i1 false) #2
ret void
}
; Function Attrs: argmemonly nounwind
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #1
attributes #0 = { nounwind "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind }
attributes #2 = { nounwind }