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ARM: improve WoA ABI conformance for frame register
Windows on ARM uses R11 for the frame pointer even though the environment is a pure Thumb-2, thumb-only environment. Replicate this behaviour to improve Windows ABI compatibility. This register is used for fast stack walking, and thus is part of the Windows ABI. llvm-svn: 209085
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@ -44,9 +44,13 @@
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using namespace llvm;
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ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti)
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: ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti),
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FramePtr((STI.isTargetMachO() || STI.isThumb()) ? ARM::R7 : ARM::R11),
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BasePtr(ARM::R6) {
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: ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), BasePtr(ARM::R6) {
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if (STI.isTargetMachO())
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FramePtr = ARM::R7;
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else if (STI.isTargetWindows())
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FramePtr = ARM::R11;
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else // ARM EABI
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FramePtr = STI.isThumb() ? ARM::R7 : ARM::R11;
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}
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const MCPhysReg*
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22
test/CodeGen/ARM/Windows/frame-register.ll
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22
test/CodeGen/ARM/Windows/frame-register.ll
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@ -0,0 +1,22 @@
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; RUN: llc -mtriple thumbv7-windows -disable-fp-elim -filetype asm -o - %s \
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; RUN: | FileCheck %s
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declare void @callee(i32)
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define i32 @calleer(i32 %i) {
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entry:
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%i.addr = alloca i32, align 4
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%j = alloca i32, align 4
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store i32 %i, i32* %i.addr, align 4
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%0 = load i32* %i.addr, align 4
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%add = add nsw i32 %0, 1
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store i32 %add, i32* %j, align 4
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%1 = load i32* %j, align 4
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call void @callee(i32 %1)
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%2 = load i32* %j, align 4
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%add1 = add nsw i32 %2, 1
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ret i32 %add1
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}
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; CHECK: push.w {r11, lr}
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38
test/CodeGen/ARM/frame-register.ll
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38
test/CodeGen/ARM/frame-register.ll
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@ -0,0 +1,38 @@
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; RUN: llc -mtriple arm-eabi -disable-fp-elim -filetype asm -o - %s \
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; RUN: | FileCheck -check-prefix CHECK-ARM %s
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; RUN: llc -mtriple thumb-eabi -disable-fp-elim -filetype asm -o - %s \
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; RUN: | FileCheck -check-prefix CHECK-THUMB %s
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; RUN: llc -mtriple arm-darwin -disable-fp-elim -filetype asm -o - %s \
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; RUN: | FileCheck -check-prefix CHECK-DARWIN-ARM %s
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; RUN: llc -mtriple thumb-darwin -disable-fp-elim -filetype asm -o - %s \
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; RUN: | FileCheck -check-prefix CHECK-DARWIN-THUMB %s
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declare void @callee(i32)
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define i32 @calleer(i32 %i) {
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entry:
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%i.addr = alloca i32, align 4
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%j = alloca i32, align 4
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store i32 %i, i32* %i.addr, align 4
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%0 = load i32* %i.addr, align 4
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%add = add nsw i32 %0, 1
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store i32 %add, i32* %j, align 4
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%1 = load i32* %j, align 4
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call void @callee(i32 %1)
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%2 = load i32* %j, align 4
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%add1 = add nsw i32 %2, 1
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ret i32 %add1
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}
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; CHECK-ARM: push {r11, lr}
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; CHECK-ARM: mov r11, sp
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; CHECK-THUMB: push {r4, r6, r7, lr}
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; CHECK-THUMB: add r7, sp, #8
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; CHECK-DARWIN-ARM: push {r7, lr}
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; CHECK-DARWIN-THUMB: push {r4, r7, lr}
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