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[Hexagon] Restore handling of expanding shuffles
Fixed bugs, added testcases. The byte-unpack is actually recognized by the DAG combiner, but the halfword-unpack it not.
This commit is contained in:
Krzysztof Parzyszek
parent
5149991497
commit
6b5a937ccd
@ -852,10 +852,10 @@ namespace llvm {
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PackMux,
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};
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OpRef concats(OpRef Va, OpRef Vb, ResultStack &Results);
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OpRef packss(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results,
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OpRef packs(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results,
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MutableArrayRef<int> NewMask, unsigned Options = None);
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OpRef packpp(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results,
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MutableArrayRef<int> NewMask);
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OpRef packp(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results,
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MutableArrayRef<int> NewMask);
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OpRef vmuxs(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
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ResultStack &Results);
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OpRef vmuxp(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
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@ -868,6 +868,7 @@ namespace llvm {
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OpRef butterfly(ShuffleMask SM, OpRef Va, ResultStack &Results);
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OpRef contracting(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results);
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OpRef expanding(ShuffleMask SM, OpRef Va, ResultStack &Results);
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OpRef perfect(ShuffleMask SM, OpRef Va, ResultStack &Results);
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bool selectVectorConstants(SDNode *N);
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@ -1114,10 +1115,12 @@ OpRef HvxSelector::concats(OpRef Lo, OpRef Hi, ResultStack &Results) {
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return OpRef::res(Results.top());
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}
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// Va, Vb are single vectors, SM is a single vector.
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OpRef HvxSelector::packss(ShuffleMask SM, OpRef Va, OpRef Vb,
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ResultStack &Results, MutableArrayRef<int> NewMask,
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unsigned Options) {
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// Va, Vb are single vectors. If SM only uses two vector halves from Va/Vb,
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// pack these halves into a single vector, and remap SM into NewMask to use
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// the new vector instead.
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OpRef HvxSelector::packs(ShuffleMask SM, OpRef Va, OpRef Vb,
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ResultStack &Results, MutableArrayRef<int> NewMask,
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unsigned Options) {
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DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
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if (!Va.isValid() || !Vb.isValid())
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return OpRef::fail();
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@ -1125,6 +1128,7 @@ OpRef HvxSelector::packss(ShuffleMask SM, OpRef Va, OpRef Vb,
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MVT Ty = getSingleVT(MVT::i8);
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MVT PairTy = getPairVT(MVT::i8);
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OpRef Inp[2] = {Va, Vb};
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unsigned VecLen = SM.Mask.size();
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auto valign = [this](OpRef Lo, OpRef Hi, unsigned Amt, MVT Ty,
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ResultStack &Results) {
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@ -1144,18 +1148,51 @@ OpRef HvxSelector::packss(ShuffleMask SM, OpRef Va, OpRef Vb,
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return OpRef::res(Results.top());
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};
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// Segment is a vector half.
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unsigned SegLen = HwLen / 2;
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// Check if we can shuffle vector halves around to get the used elements
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// into a single vector.
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SmallVector<int,128> MaskH(SM.Mask.begin(), SM.Mask.end());
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SmallVector<unsigned, 4> SegList = getInputSegmentList(SM.Mask, HwLen/2);
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SmallVector<unsigned, 4> SegList = getInputSegmentList(SM.Mask, SegLen);
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unsigned SegCount = SegList.size();
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SmallVector<unsigned, 4> SegMap = getOutputSegmentMap(SM.Mask, SegLen);
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if (SegList.empty())
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return OpRef::undef(Ty);
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// NOTE:
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// In the following part of the function, where the segments are rearranged,
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// the shuffle mask SM can be of any length that is a multiple of a vector
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// (i.e. a multiple of 2*SegLen), and non-zero.
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// The output segment map is computed, and it may have any even number of
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// entries, but the rearrangement of input segments will be done based only
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// on the first two (non-undef) entries in the segment map.
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// For example, if the output map is 3, 1, 1, 3 (it can have at most two
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// distinct entries!), the segments 1 and 3 of Va/Vb will be packaged into
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// a single vector V = 3:1. The output mask will then be updated to use
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// seg(0,V), seg(1,V), seg(1,V), seg(0,V).
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//
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// Picking the segments based on the output map is an optimization. For
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// correctness it is only necessary that Seg0 and Seg1 are the two input
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// segments that are used in the output.
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unsigned Seg0 = ~0u, Seg1 = ~0u;
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for (int I = 0, E = SegMap.size(); I != E; ++I) {
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unsigned X = SegMap[I];
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if (X == ~0u)
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continue;
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if (Seg0 == ~0u)
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Seg0 = X;
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else if (Seg1 != ~0u)
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break;
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if (X == ~1u || X != Seg0)
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Seg1 = X;
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}
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if (SegCount == 1) {
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unsigned SrcOp = SegList[0] / 2;
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for (int I = 0, E = SM.Mask.size(); I != E; ++I) {
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for (int I = 0; I != static_cast<int>(VecLen); ++I) {
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int M = SM.Mask[I];
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if (M >= 0) {
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M -= SrcOp * HwLen;
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@ -1167,58 +1204,69 @@ OpRef HvxSelector::packss(ShuffleMask SM, OpRef Va, OpRef Vb,
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}
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if (SegCount == 2) {
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SmallVector<unsigned, 4> SegMap = getOutputSegmentMap(SM.Mask, HwLen/2);
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unsigned Seg0 = SegMap[0], Seg1 = SegMap[1];
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// Seg0 should not be undef here: this would imply a SegList
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// with <= 1 elements, which was checked earlier.
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assert(Seg0 != ~0u);
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// Both output segments shouldn't be undef here: this would imply
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// empty SegList, which was checked above.
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assert(Seg0 != ~0u || Seg1 != ~0u);
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if (Seg0 != ~1u && Seg1 != ~1u) {
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const SDLoc &dl(Results.InpNode);
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Results.push(Hexagon::A2_tfrsi, MVT::i32, {getConst32(HwLen/2, dl)});
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OpRef HL = OpRef::res(Results.top());
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// Va = AB, Vb = CD
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if (Seg0 / 2 == Seg1 / 2) {
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// Same input vector.
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Va = Inp[Seg0 / 2];
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if (Seg0 > Seg1) {
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// Swap halves.
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Results.push(Hexagon::V6_vror, Ty, {Inp[Seg0 / 2], HL});
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Va = OpRef::res(Results.top());
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}
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packSegmentMask(SM.Mask, SegMap, HwLen/2, MaskH);
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} else if (Seg0 % 2 == Seg1 % 2) {
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// Picking AC, BD, CA, or DB.
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// vshuff(CD,AB,HL) -> BD:AC
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// vshuff(AB,CD,HL) -> DB:CA
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auto Vs = (Seg0 == 0 || Seg0 == 1) ? std::make_pair(Vb, Va) // AC or BD
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: std::make_pair(Va, Vb); // CA or DB
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Results.push(Hexagon::V6_vshuffvdd, PairTy, {Vs.first, Vs.second, HL});
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OpRef P = OpRef::res(Results.top());
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Va = (Seg0 == 0 || Seg0 == 2) ? OpRef::lo(P) : OpRef::hi(P);
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packSegmentMask(SM.Mask, SegMap, HwLen/2, MaskH);
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// If Seg0 or Seg1 are "multi-defined", pick them from the input
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// segment list instead.
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if (Seg0 == ~1u || Seg1 == ~1u) {
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if (Seg0 == Seg1) {
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Seg0 = SegList[0];
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Seg1 = SegList[1];
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} else if (Seg0 == ~1u) {
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Seg0 = SegList[0] != Seg1 ? SegList[0] : SegList[1];
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} else {
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// Picking AD, BC, CB, or DA.
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if ((Seg0 == 0 && Seg1 == 3) || (Seg0 == 2 && Seg1 == 1)) {
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// AD or BC: this can be done using vmux.
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// Q = V6_pred_scalar2 HwLen/2
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// V = V6_vmux Q, (Va, Vb) or (Vb, Va)
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Results.push(Hexagon::V6_pred_scalar2, getBoolVT(), {HL});
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OpRef Qt = OpRef::res(Results.top());
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auto Vs = (Seg0 == 0) ? std::make_pair(Va, Vb) // AD
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: std::make_pair(Vb, Va); // CB
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Results.push(Hexagon::V6_vmux, Ty, {Qt, Vs.first, Vs.second});
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Va = OpRef::res(Results.top());
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packSegmentMask(SM.Mask, SegMap, HwLen/2, MaskH);
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} else {
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// BC or DA: this could be done via valign by HwLen/2.
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// Do nothing here, because valign (if possible) will be generated
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// later on (make sure the Seg0 values are as expected, for sanity).
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assert(Seg0 == 1 || Seg0 == 3);
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}
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assert(Seg1 == ~1u); // Sanity
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Seg1 = SegList[0] != Seg0 ? SegList[0] : SegList[1];
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}
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}
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assert(Seg0 != ~1u && Seg1 != ~1u);
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assert(Seg0 != Seg1 && "Expecting different segments");
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const SDLoc &dl(Results.InpNode);
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Results.push(Hexagon::A2_tfrsi, MVT::i32, {getConst32(SegLen, dl)});
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OpRef HL = OpRef::res(Results.top());
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// Va = AB, Vb = CD
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if (Seg0 / 2 == Seg1 / 2) {
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// Same input vector.
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Va = Inp[Seg0 / 2];
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if (Seg0 > Seg1) {
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// Swap halves.
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Results.push(Hexagon::V6_vror, Ty, {Inp[Seg0 / 2], HL});
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Va = OpRef::res(Results.top());
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}
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packSegmentMask(SM.Mask, {Seg0, Seg1}, SegLen, MaskH);
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} else if (Seg0 % 2 == Seg1 % 2) {
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// Picking AC, BD, CA, or DB.
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// vshuff(CD,AB,HL) -> BD:AC
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// vshuff(AB,CD,HL) -> DB:CA
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auto Vs = (Seg0 == 0 || Seg0 == 1) ? std::make_pair(Vb, Va) // AC or BD
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: std::make_pair(Va, Vb); // CA or DB
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Results.push(Hexagon::V6_vshuffvdd, PairTy, {Vs.first, Vs.second, HL});
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OpRef P = OpRef::res(Results.top());
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Va = (Seg0 == 0 || Seg0 == 2) ? OpRef::lo(P) : OpRef::hi(P);
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packSegmentMask(SM.Mask, {Seg0, Seg1}, SegLen, MaskH);
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} else {
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// Picking AD, BC, CB, or DA.
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if ((Seg0 == 0 && Seg1 == 3) || (Seg0 == 2 && Seg1 == 1)) {
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// AD or BC: this can be done using vmux.
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// Q = V6_pred_scalar2 SegLen
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// V = V6_vmux Q, (Va, Vb) or (Vb, Va)
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Results.push(Hexagon::V6_pred_scalar2, getBoolVT(), {HL});
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OpRef Qt = OpRef::res(Results.top());
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auto Vs = (Seg0 == 0) ? std::make_pair(Va, Vb) // AD
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: std::make_pair(Vb, Va); // CB
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Results.push(Hexagon::V6_vmux, Ty, {Qt, Vs.first, Vs.second});
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Va = OpRef::res(Results.top());
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packSegmentMask(SM.Mask, {Seg0, Seg1}, SegLen, MaskH);
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} else {
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// BC or DA: this could be done via valign by SegLen.
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// Do nothing here, because valign (if possible) will be generated
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// later on (make sure the Seg0 values are as expected, for sanity).
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assert(Seg0 == 1 || Seg0 == 3);
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}
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}
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}
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@ -1226,6 +1274,7 @@ OpRef HvxSelector::packss(ShuffleMask SM, OpRef Va, OpRef Vb,
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// Check if the arguments can be packed by valign(Va,Vb) or valign(Vb,Va).
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ShuffleMask SMH(MaskH);
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assert(SMH.Mask.size() == VecLen);
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SmallVector<int,128> MaskA(SMH.Mask.begin(), SMH.Mask.end());
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if (SMH.MaxSrc - SMH.MinSrc >= static_cast<int>(HwLen)) {
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@ -1239,6 +1288,7 @@ OpRef HvxSelector::packss(ShuffleMask SM, OpRef Va, OpRef Vb,
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}
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}
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ShuffleMask SMA(MaskA);
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assert(SMA.Mask.size() == VecLen);
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if (SMA.MaxSrc - SMA.MinSrc < static_cast<int>(HwLen)) {
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int ShiftR = SMA.MinSrc;
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@ -1249,7 +1299,7 @@ OpRef HvxSelector::packss(ShuffleMask SM, OpRef Va, OpRef Vb,
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}
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OpRef RetVal = valign(Va, Vb, ShiftR, Ty, Results);
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for (int I = 0, E = SMA.Mask.size(); I != E; ++I) {
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for (int I = 0; I != static_cast<int>(VecLen); ++I) {
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int M = SMA.Mask[I];
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if (M != -1)
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M -= SMA.MinSrc;
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@ -1269,7 +1319,7 @@ OpRef HvxSelector::packss(ShuffleMask SM, OpRef Va, OpRef Vb,
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BitVector Picked(HwLen);
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SmallVector<uint8_t,128> MuxBytes(HwLen);
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bool CanMux = true;
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for (int I = 0, E = SM.Mask.size(); I != E; ++I) {
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for (int I = 0; I != static_cast<int>(VecLen); ++I) {
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int M = SM.Mask[I];
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if (M == -1)
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continue;
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@ -1289,9 +1339,11 @@ OpRef HvxSelector::packss(ShuffleMask SM, OpRef Va, OpRef Vb,
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return OpRef::fail();
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}
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// Va, Vb are vector pairs, SM is a vector pair.
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OpRef HvxSelector::packpp(ShuffleMask SM, OpRef Va, OpRef Vb,
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ResultStack &Results, MutableArrayRef<int> NewMask) {
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// Va, Vb are vector pairs. If SM only uses two single vectors from Va/Vb,
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// pack these vectors into a pair, and remap SM into NewMask to use the
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// new pair instead.
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OpRef HvxSelector::packp(ShuffleMask SM, OpRef Va, OpRef Vb,
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ResultStack &Results, MutableArrayRef<int> NewMask) {
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DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
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SmallVector<unsigned, 4> SegList = getInputSegmentList(SM.Mask, HwLen);
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if (SegList.empty())
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@ -1320,7 +1372,7 @@ OpRef HvxSelector::packpp(ShuffleMask SM, OpRef Va, OpRef Vb,
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// NOTE: Using SegList as the packing map here (not SegMap). This works,
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// because we're not concerned here about the order of the segments (i.e.
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// single vectors) in the output pair. Changing the order of vectors is
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// free (as opposed to changing the order of vector halves as in packss),
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// free (as opposed to changing the order of vector halves as in packs),
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// and so there is no extra cost added in case the order needs to be
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// changed later.
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packSegmentMask(SM.Mask, SegList, HwLen, NewMask);
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@ -1398,7 +1450,7 @@ OpRef HvxSelector::shuffs2(ShuffleMask SM, OpRef Va, OpRef Vb,
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int VecLen = SM.Mask.size();
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SmallVector<int,128> PackedMask(VecLen);
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OpRef P = packss(SM, Va, Vb, Results, PackedMask);
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OpRef P = packs(SM, Va, Vb, Results, PackedMask);
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if (P.isValid())
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return shuffs1(ShuffleMask(PackedMask), P, Results);
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@ -1424,12 +1476,27 @@ OpRef HvxSelector::shuffs2(ShuffleMask SM, OpRef Va, OpRef Vb,
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OpRef HvxSelector::shuffp1(ShuffleMask SM, OpRef Va, ResultStack &Results) {
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DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
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int VecLen = SM.Mask.size();
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if (isIdentity(SM.Mask))
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return Va;
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if (isUndef(SM.Mask))
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return OpRef::undef(getPairVT(MVT::i8));
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SmallVector<int,128> PackedMask(VecLen);
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OpRef P = packs(SM, OpRef::lo(Va), OpRef::hi(Va), Results, PackedMask);
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if (P.isValid()) {
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ShuffleMask PM(PackedMask);
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OpRef E = expanding(PM, P, Results);
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if (E.isValid())
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return E;
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OpRef L = shuffs1(PM.lo(), P, Results);
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OpRef H = shuffs1(PM.hi(), P, Results);
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if (L.isValid() && H.isValid())
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return concats(L, H, Results);
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}
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OpRef R = perfect(SM, Va, Results);
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if (R.isValid())
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return R;
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@ -1451,7 +1518,7 @@ OpRef HvxSelector::shuffp2(ShuffleMask SM, OpRef Va, OpRef Vb,
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int VecLen = SM.Mask.size();
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SmallVector<int,256> PackedMask(VecLen);
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OpRef P = packpp(SM, Va, Vb, Results, PackedMask);
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OpRef P = packp(SM, Va, Vb, Results, PackedMask);
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if (P.isValid())
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return shuffp1(ShuffleMask(PackedMask), P, Results);
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@ -1776,6 +1843,60 @@ OpRef HvxSelector::contracting(ShuffleMask SM, OpRef Va, OpRef Vb,
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return OpRef::res(Results.top());
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}
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OpRef HvxSelector::expanding(ShuffleMask SM, OpRef Va, ResultStack &Results) {
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DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
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// Expanding shuffles (using all elements and inserting into larger vector):
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//
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// V6_vunpacku{b,h} [*]
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//
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// [*] Only if the upper elements (filled with 0s) are "don't care" in Mask.
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//
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// Note: V6_vunpacko{b,h} are or-ing the high byte/half in the result, so
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// they are not shuffles.
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//
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// The argument is a single vector.
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int VecLen = SM.Mask.size();
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assert(2*HwLen == unsigned(VecLen) && "Expecting vector-pair type");
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std::pair<int,unsigned> Strip = findStrip(SM.Mask, 1, VecLen);
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// The patterns for the unpacks, in terms of the starting offsets of the
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// consecutive strips (L = length of the strip, N = VecLen):
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//
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// vunpacku: 0, -1, L, -1, 2L, -1 ...
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if (Strip.first != 0)
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return OpRef::fail();
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// The vunpackus only handle byte and half-word.
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if (Strip.second != 1 && Strip.second != 2)
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return OpRef::fail();
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int N = VecLen;
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int L = Strip.second;
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// First, check the non-ignored strips.
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for (int I = 2*L; I < N; I += 2*L) {
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auto S = findStrip(SM.Mask.drop_front(I), 1, N-I);
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if (S.second != unsigned(L))
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return OpRef::fail();
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if (2*S.first != I)
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return OpRef::fail();
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}
|
||||
// Check the -1s.
|
||||
for (int I = L; I < N; I += 2*L) {
|
||||
auto S = findStrip(SM.Mask.drop_front(I), 0, N-I);
|
||||
if (S.first != -1 || S.second != unsigned(L))
|
||||
return OpRef::fail();
|
||||
}
|
||||
|
||||
unsigned Opc = Strip.second == 1 ? Hexagon::V6_vunpackub
|
||||
: Hexagon::V6_vunpackuh;
|
||||
Results.push(Opc, getPairVT(MVT::i8), {Va});
|
||||
return OpRef::res(Results.top());
|
||||
}
|
||||
|
||||
OpRef HvxSelector::perfect(ShuffleMask SM, OpRef Va, ResultStack &Results) {
|
||||
DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
|
||||
// V6_vdeal{b,h}
|
||||
|
||||
28
test/CodeGen/Hexagon/autohvx/shuffle-expanding-128b.ll
Normal file
28
test/CodeGen/Hexagon/autohvx/shuffle-expanding-128b.ll
Normal file
@ -0,0 +1,28 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
|
||||
define <256 x i8> @f0(<128 x i8> %a0) #0 {
|
||||
; CHECK-LABEL: f0:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1:0.uh = vunpack(v0.ub)
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = shufflevector <128 x i8> %a0, <128 x i8> undef, <256 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef, i32 8, i32 undef, i32 9, i32 undef, i32 10, i32 undef, i32 11, i32 undef, i32 12, i32 undef, i32 13, i32 undef, i32 14, i32 undef, i32 15, i32 undef, i32 16, i32 undef, i32 17, i32 undef, i32 18, i32 undef, i32 19, i32 undef, i32 20, i32 undef, i32 21, i32 undef, i32 22, i32 undef, i32 23, i32 undef, i32 24, i32 undef, i32 25, i32 undef, i32 26, i32 undef, i32 27, i32 undef, i32 28, i32 undef, i32 29, i32 undef, i32 30, i32 undef, i32 31, i32 undef, i32 32, i32 undef, i32 33, i32 undef, i32 34, i32 undef, i32 35, i32 undef, i32 36, i32 undef, i32 37, i32 undef, i32 38, i32 undef, i32 39, i32 undef, i32 40, i32 undef, i32 41, i32 undef, i32 42, i32 undef, i32 43, i32 undef, i32 44, i32 undef, i32 45, i32 undef, i32 46, i32 undef, i32 47, i32 undef, i32 48, i32 undef, i32 49, i32 undef, i32 50, i32 undef, i32 51, i32 undef, i32 52, i32 undef, i32 53, i32 undef, i32 54, i32 undef, i32 55, i32 undef, i32 56, i32 undef, i32 57, i32 undef, i32 58, i32 undef, i32 59, i32 undef, i32 60, i32 undef, i32 61, i32 undef, i32 62, i32 undef, i32 63, i32 undef, i32 64, i32 undef, i32 65, i32 undef, i32 66, i32 undef, i32 67, i32 undef, i32 68, i32 undef, i32 69, i32 undef, i32 70, i32 undef, i32 71, i32 undef, i32 72, i32 undef, i32 73, i32 undef, i32 74, i32 undef, i32 75, i32 undef, i32 76, i32 undef, i32 77, i32 undef, i32 78, i32 undef, i32 79, i32 undef, i32 80, i32 undef, i32 81, i32 undef, i32 82, i32 undef, i32 83, i32 undef, i32 84, i32 undef, i32 85, i32 undef, i32 86, i32 undef, i32 87, i32 undef, i32 88, i32 undef, i32 89, i32 undef, i32 90, i32 undef, i32 91, i32 undef, i32 92, i32 undef, i32 93, i32 undef, i32 94, i32 undef, i32 95, i32 undef, i32 96, i32 undef, i32 97, i32 undef, i32 98, i32 undef, i32 99, i32 undef, i32 100, i32 undef, i32 101, i32 undef, i32 102, i32 undef, i32 103, i32 undef, i32 104, i32 undef, i32 105, i32 undef, i32 106, i32 undef, i32 107, i32 undef, i32 108, i32 undef, i32 109, i32 undef, i32 110, i32 undef, i32 111, i32 undef, i32 112, i32 undef, i32 113, i32 undef, i32 114, i32 undef, i32 115, i32 undef, i32 116, i32 undef, i32 117, i32 undef, i32 118, i32 undef, i32 119, i32 undef, i32 120, i32 undef, i32 121, i32 undef, i32 122, i32 undef, i32 123, i32 undef, i32 124, i32 undef, i32 125, i32 undef, i32 126, i32 undef, i32 127, i32 undef>
|
||||
ret <256 x i8> %v0
|
||||
}
|
||||
|
||||
|
||||
define <256 x i8> @f1(<128 x i8> %a0) #0 {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1:0.uw = vunpack(v0.uh)
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = shufflevector <128 x i8> %a0, <128 x i8> undef, <256 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 2, i32 3, i32 undef, i32 undef, i32 4, i32 5, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 undef, i32 8, i32 9, i32 undef, i32 undef, i32 10, i32 11, i32 undef, i32 undef, i32 12, i32 13, i32 undef, i32 undef, i32 14, i32 15, i32 undef, i32 undef, i32 16, i32 17, i32 undef, i32 undef, i32 18, i32 19, i32 undef, i32 undef, i32 20, i32 21, i32 undef, i32 undef, i32 22, i32 23, i32 undef, i32 undef, i32 24, i32 25, i32 undef, i32 undef, i32 26, i32 27, i32 undef, i32 undef, i32 28, i32 29, i32 undef, i32 undef, i32 30, i32 31, i32 undef, i32 undef, i32 32, i32 33, i32 undef, i32 undef, i32 34, i32 35, i32 undef, i32 undef, i32 36, i32 37, i32 undef, i32 undef, i32 38, i32 39, i32 undef, i32 undef, i32 40, i32 41, i32 undef, i32 undef, i32 42, i32 43, i32 undef, i32 undef, i32 44, i32 45, i32 undef, i32 undef, i32 46, i32 47, i32 undef, i32 undef, i32 48, i32 49, i32 undef, i32 undef, i32 50, i32 51, i32 undef, i32 undef, i32 52, i32 53, i32 undef, i32 undef, i32 54, i32 55, i32 undef, i32 undef, i32 56, i32 57, i32 undef, i32 undef, i32 58, i32 59, i32 undef, i32 undef, i32 60, i32 61, i32 undef, i32 undef, i32 62, i32 63, i32 undef, i32 undef, i32 64, i32 65, i32 undef, i32 undef, i32 66, i32 67, i32 undef, i32 undef, i32 68, i32 69, i32 undef, i32 undef, i32 70, i32 71, i32 undef, i32 undef, i32 72, i32 73, i32 undef, i32 undef, i32 74, i32 75, i32 undef, i32 undef, i32 76, i32 77, i32 undef, i32 undef, i32 78, i32 79, i32 undef, i32 undef, i32 80, i32 81, i32 undef, i32 undef, i32 82, i32 83, i32 undef, i32 undef, i32 84, i32 85, i32 undef, i32 undef, i32 86, i32 87, i32 undef, i32 undef, i32 88, i32 89, i32 undef, i32 undef, i32 90, i32 91, i32 undef, i32 undef, i32 92, i32 93, i32 undef, i32 undef, i32 94, i32 95, i32 undef, i32 undef, i32 96, i32 97, i32 undef, i32 undef, i32 98, i32 99, i32 undef, i32 undef, i32 100, i32 101, i32 undef, i32 undef, i32 102, i32 103, i32 undef, i32 undef, i32 104, i32 105, i32 undef, i32 undef, i32 106, i32 107, i32 undef, i32 undef, i32 108, i32 109, i32 undef, i32 undef, i32 110, i32 111, i32 undef, i32 undef, i32 112, i32 113, i32 undef, i32 undef, i32 114, i32 115, i32 undef, i32 undef, i32 116, i32 117, i32 undef, i32 undef, i32 118, i32 119, i32 undef, i32 undef, i32 120, i32 121, i32 undef, i32 undef, i32 122, i32 123, i32 undef, i32 undef, i32 124, i32 125, i32 undef, i32 undef, i32 126, i32 127, i32 undef, i32 undef>
|
||||
ret <256 x i8> %v0
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone "target-features"="+hvx,+hvx-length128b" }
|
||||
|
||||
28
test/CodeGen/Hexagon/autohvx/shuffle-expanding-64b.ll
Normal file
28
test/CodeGen/Hexagon/autohvx/shuffle-expanding-64b.ll
Normal file
@ -0,0 +1,28 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
|
||||
define <128 x i8> @f0(<64 x i8> %a0) #0 {
|
||||
; CHECK-LABEL: f0:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1:0.uh = vunpack(v0.ub)
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = shufflevector <64 x i8> %a0, <64 x i8> undef, <128 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef, i32 8, i32 undef, i32 9, i32 undef, i32 10, i32 undef, i32 11, i32 undef, i32 12, i32 undef, i32 13, i32 undef, i32 14, i32 undef, i32 15, i32 undef, i32 16, i32 undef, i32 17, i32 undef, i32 18, i32 undef, i32 19, i32 undef, i32 20, i32 undef, i32 21, i32 undef, i32 22, i32 undef, i32 23, i32 undef, i32 24, i32 undef, i32 25, i32 undef, i32 26, i32 undef, i32 27, i32 undef, i32 28, i32 undef, i32 29, i32 undef, i32 30, i32 undef, i32 31, i32 undef, i32 32, i32 undef, i32 33, i32 undef, i32 34, i32 undef, i32 35, i32 undef, i32 36, i32 undef, i32 37, i32 undef, i32 38, i32 undef, i32 39, i32 undef, i32 40, i32 undef, i32 41, i32 undef, i32 42, i32 undef, i32 43, i32 undef, i32 44, i32 undef, i32 45, i32 undef, i32 46, i32 undef, i32 47, i32 undef, i32 48, i32 undef, i32 49, i32 undef, i32 50, i32 undef, i32 51, i32 undef, i32 52, i32 undef, i32 53, i32 undef, i32 54, i32 undef, i32 55, i32 undef, i32 56, i32 undef, i32 57, i32 undef, i32 58, i32 undef, i32 59, i32 undef, i32 60, i32 undef, i32 61, i32 undef, i32 62, i32 undef, i32 63, i32 undef>
|
||||
ret <128 x i8> %v0
|
||||
}
|
||||
|
||||
|
||||
define <128 x i8> @f1(<64 x i8> %a0) #0 {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1:0.uw = vunpack(v0.uh)
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = shufflevector <64 x i8> %a0, <64 x i8> undef, <128 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 2, i32 3, i32 undef, i32 undef, i32 4, i32 5, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 undef, i32 8, i32 9, i32 undef, i32 undef, i32 10, i32 11, i32 undef, i32 undef, i32 12, i32 13, i32 undef, i32 undef, i32 14, i32 15, i32 undef, i32 undef, i32 16, i32 17, i32 undef, i32 undef, i32 18, i32 19, i32 undef, i32 undef, i32 20, i32 21, i32 undef, i32 undef, i32 22, i32 23, i32 undef, i32 undef, i32 24, i32 25, i32 undef, i32 undef, i32 26, i32 27, i32 undef, i32 undef, i32 28, i32 29, i32 undef, i32 undef, i32 30, i32 31, i32 undef, i32 undef, i32 32, i32 33, i32 undef, i32 undef, i32 34, i32 35, i32 undef, i32 undef, i32 36, i32 37, i32 undef, i32 undef, i32 38, i32 39, i32 undef, i32 undef, i32 40, i32 41, i32 undef, i32 undef, i32 42, i32 43, i32 undef, i32 undef, i32 44, i32 45, i32 undef, i32 undef, i32 46, i32 47, i32 undef, i32 undef, i32 48, i32 49, i32 undef, i32 undef, i32 50, i32 51, i32 undef, i32 undef, i32 52, i32 53, i32 undef, i32 undef, i32 54, i32 55, i32 undef, i32 undef, i32 56, i32 57, i32 undef, i32 undef, i32 58, i32 59, i32 undef, i32 undef, i32 60, i32 61, i32 undef, i32 undef, i32 62, i32 63, i32 undef, i32 undef>
|
||||
ret <128 x i8> %v0
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone "target-features"="+hvx,+hvx-length64b" }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user