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[X86] Remove MMX_MASKMOVQ64 and VMASKMOVDQU from scheduler models.

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The information was so wildly inaccurate and incomplete its better to just remove it.

MMX_MASKMOVQ64 showed up twice in several scheduler models. In Haswell and Broadwell they were on adjacent lines. On Skylake the copies had different information.

MMX_MASKMOVQ and MASKMOVDQU were completely missing.

MMX_MASKMOVQ64 was listed on Haswell/Broadwell as 1 cycle on port 1 despite it being a store instruction.

Filed PR36780 to track fixing this right.

llvm-svn: 327783
This commit is contained in:
Craig Topper 2018-03-18 03:24:42 +00:00
parent bb9cb03ed3
commit 6b5dda1657
5 changed files with 2 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/X86/X86SchedBroadwell.td
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@ -385,11 +385,8 @@ def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
}
def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r")>;
def: InstRW<[BWWriteResGroup2], (instregex "COM_FST0r")>;
def: InstRW<[BWWriteResGroup2], (instregex "MMX_MASKMOVQ64")>;
def: InstRW<[BWWriteResGroup2], (instregex "MMX_MASKMOVQ64")>;
def: InstRW<[BWWriteResGroup2], (instregex "UCOM_FPr")>;
def: InstRW<[BWWriteResGroup2], (instregex "UCOM_Fr")>;
def: InstRW<[BWWriteResGroup2], (instregex "VMASKMOVDQU")>;
def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
let Latency = 1;

3
lib/Target/X86/X86SchedHaswell.td
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@ -953,11 +953,8 @@ def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {
}
def: InstRW<[HWWriteResGroup3], (instregex "COMP_FST0r")>;
def: InstRW<[HWWriteResGroup3], (instregex "COM_FST0r")>;
def: InstRW<[HWWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;
def: InstRW<[HWWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;
def: InstRW<[HWWriteResGroup3], (instregex "UCOM_FPr")>;
def: InstRW<[HWWriteResGroup3], (instregex "UCOM_Fr")>;
def: InstRW<[HWWriteResGroup3], (instregex "VMASKMOVDQU")>;
def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {
let Latency = 1;

9
lib/Target/X86/X86SchedSkylakeClient.td
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@ -357,13 +357,6 @@ def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBSWirr")>;
def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBUSBirr")>;
def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBUSWirr")>;
def SKLWriteResGroup2 : SchedWriteRes<[SKLPort1]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup2], (instregex "MMX_MASKMOVQ64")>;
def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
let Latency = 1;
let NumMicroOps = 1;
@ -1097,8 +1090,6 @@ def SKLWriteResGroup18 : SchedWriteRes<[SKLPort0,SKLPort237]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup18], (instregex "MMX_MASKMOVQ64")>;
def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVDQU")>;
def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPDYmr")>;
def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPDmr")>;
def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPSYmr")>;

9
lib/Target/X86/X86SchedSkylakeServer.td
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@ -397,13 +397,6 @@ def: InstRW<[SKXWriteResGroup1], (instregex "VPMOVW2MZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup1], (instregex "VPMOVW2MZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup1], (instregex "VPMOVW2MZrr(b?)(k?)(z?)")>;
def SKXWriteResGroup2 : SchedWriteRes<[SKXPort1]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup2], (instregex "MMX_MASKMOVQ64")>;
def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
let Latency = 1;
let NumMicroOps = 1;
@ -1599,8 +1592,6 @@ def SKXWriteResGroup18 : SchedWriteRes<[SKXPort0,SKXPort237]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup18], (instregex "MMX_MASKMOVQ64")>;
def: InstRW<[SKXWriteResGroup18], (instregex "VMASKMOVDQU")>;
def: InstRW<[SKXWriteResGroup18], (instregex "VMASKMOVPDYmr")>;
def: InstRW<[SKXWriteResGroup18], (instregex "VMASKMOVPDmr")>;
def: InstRW<[SKXWriteResGroup18], (instregex "VMASKMOVPSYmr")>;

4
test/CodeGen/X86/sse2-schedule.ll
View File

@ -2236,12 +2236,12 @@ define void @test_maskmovdqu(<16 x i8> %a0, <16 x i8> %a1, i8* %a2) {
;
; SKYLAKE-LABEL: test_maskmovdqu:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [2:1.00]
; SKYLAKE-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [1:1.00]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maskmovdqu:
; SKX: # %bb.0:
; SKX-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [2:1.00]
; SKX-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [1:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_maskmovdqu: