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Revert r336950 and r336951 "[X86] Add AVX512 equivalents of some isel patterns so we get EVEX instructions." and "foo"

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One of them had a bad title and they should have been squashed.

llvm-svn: 336953
This commit is contained in:
Craig Topper 2018-07-12 21:58:03 +00:00
parent 83ad87a600
commit 6b6c56db23
6 changed files with 35 additions and 86 deletions
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39
lib/Target/X86/X86InstrAVX512.td
View File

@ -11484,13 +11484,13 @@ multiclass AVX512_scalar_math_fp_patterns<SDNode Op, string OpcPrefix, SDNode Mo
def : Pat<(_.VT (MoveNode (_.VT VR128X:$dst), (_.VT (scalar_to_vector def : Pat<(_.VT (MoveNode (_.VT VR128X:$dst), (_.VT (scalar_to_vector
(Op (_.EltVT (extractelt (_.VT VR128X:$dst), (iPTR 0))), (Op (_.EltVT (extractelt (_.VT VR128X:$dst), (iPTR 0))),
_.FRC:$src))))), _.FRC:$src))))),
(!cast<Instruction>("V"#OpcPrefix#Zrr_Int) _.VT:$dst, (!cast<I>("V"#OpcPrefix#Zrr_Int) _.VT:$dst,
(COPY_TO_REGCLASS _.FRC:$src, VR128X))>; (COPY_TO_REGCLASS _.FRC:$src, VR128X))>;
// vector math op with insert via movss // vector math op with insert via movss
def : Pat<(_.VT (MoveNode (_.VT VR128X:$dst), def : Pat<(_.VT (MoveNode (_.VT VR128X:$dst),
(Op (_.VT VR128X:$dst), (_.VT VR128X:$src)))), (Op (_.VT VR128X:$dst), (_.VT VR128X:$src)))),
(!cast<Instruction>("V"#OpcPrefix#Zrr_Int) _.VT:$dst, _.VT:$src)>; (!cast<I>("V"#OpcPrefix#Zrr_Int) _.VT:$dst, _.VT:$src)>;
// extracted masked scalar math op with insert via movss // extracted masked scalar math op with insert via movss
def : Pat<(MoveNode (_.VT VR128X:$src1), def : Pat<(MoveNode (_.VT VR128X:$src1),
@ -11499,7 +11499,7 @@ multiclass AVX512_scalar_math_fp_patterns<SDNode Op, string OpcPrefix, SDNode Mo
(Op (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), (Op (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
_.FRC:$src2), _.FRC:$src2),
_.FRC:$src0))), _.FRC:$src0))),
(!cast<Instruction>("V"#OpcPrefix#Zrr_Intk) (COPY_TO_REGCLASS _.FRC:$src0, VR128X), (!cast<I>("V"#OpcPrefix#Zrr_Intk) (COPY_TO_REGCLASS _.FRC:$src0, VR128X),
VK1WM:$mask, _.VT:$src1, VK1WM:$mask, _.VT:$src1,
(COPY_TO_REGCLASS _.FRC:$src2, VR128X))>; (COPY_TO_REGCLASS _.FRC:$src2, VR128X))>;
@ -11509,7 +11509,7 @@ multiclass AVX512_scalar_math_fp_patterns<SDNode Op, string OpcPrefix, SDNode Mo
(X86selects VK1WM:$mask, (X86selects VK1WM:$mask,
(Op (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), (Op (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
_.FRC:$src2), (_.EltVT ZeroFP)))), _.FRC:$src2), (_.EltVT ZeroFP)))),
(!cast<Instruction>("V"#OpcPrefix#Zrr_Intkz) (!cast<I>("V"#OpcPrefix#Zrr_Intkz)
VK1WM:$mask, _.VT:$src1, VK1WM:$mask, _.VT:$src1,
(COPY_TO_REGCLASS _.FRC:$src2, VR128X))>; (COPY_TO_REGCLASS _.FRC:$src2, VR128X))>;
} }
@ -11525,37 +11525,6 @@ defm : AVX512_scalar_math_fp_patterns<fsub, "SUBSD", X86Movsd, v2f64x_info, fp64
defm : AVX512_scalar_math_fp_patterns<fmul, "MULSD", X86Movsd, v2f64x_info, fp64imm0>; defm : AVX512_scalar_math_fp_patterns<fmul, "MULSD", X86Movsd, v2f64x_info, fp64imm0>;
defm : AVX512_scalar_math_fp_patterns<fdiv, "DIVSD", X86Movsd, v2f64x_info, fp64imm0>; defm : AVX512_scalar_math_fp_patterns<fdiv, "DIVSD", X86Movsd, v2f64x_info, fp64imm0>;
multiclass AVX512_scalar_unary_math_patterns<SDNode OpNode, string OpcPrefix,
SDNode Move, X86VectorVTInfo _> {
let Predicates = [HasAVX512] in {
def : Pat<(_.VT (Move _.VT:$dst,
(scalar_to_vector (OpNode (extractelt _.VT:$src, 0))))),
(!cast<Instruction>("V"#OpcPrefix#Zr_Int) _.VT:$dst, _.VT:$src)>;
}
}
defm : AVX512_scalar_unary_math_patterns<fsqrt, "SQRTSS", X86Movss, v4f32x_info>;
defm : AVX512_scalar_unary_math_patterns<fsqrt, "SQRTSD", X86Movsd, v2f64x_info>;
multiclass AVX512_scalar_unary_math_imm_patterns<SDNode OpNode, string OpcPrefix,
SDNode Move, X86VectorVTInfo _,
bits<8> ImmV> {
let Predicates = [HasAVX512] in {
def : Pat<(_.VT (Move _.VT:$dst,
(scalar_to_vector (OpNode (extractelt _.VT:$src, 0))))),
(!cast<Instruction>("V"#OpcPrefix#Zr_Int) _.VT:$dst, _.VT:$src,
(i32 ImmV))>;
}
}
defm : AVX512_scalar_unary_math_imm_patterns<ffloor, "RNDSCALESS", X86Movss,
v4f32x_info, 0x01>;
defm : AVX512_scalar_unary_math_imm_patterns<fceil, "RNDSCALESS", X86Movss,
v4f32x_info, 0x02>;
defm : AVX512_scalar_unary_math_imm_patterns<ffloor, "RNDSCALESD", X86Movsd,
v2f64x_info, 0x01>;
defm : AVX512_scalar_unary_math_imm_patterns<fceil, "RNDSCALESD", X86Movsd,
v2f64x_info, 0x02>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// AES instructions // AES instructions

24
lib/Target/X86/X86InstrSSE.td
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@ -2647,13 +2647,13 @@ multiclass scalar_math_patterns<SDNode Op, string OpcPrefix, SDNode Move,
def : Pat<(VT (Move (VT VR128:$dst), (VT (scalar_to_vector def : Pat<(VT (Move (VT VR128:$dst), (VT (scalar_to_vector
(Op (EltTy (extractelt (VT VR128:$dst), (iPTR 0))), (Op (EltTy (extractelt (VT VR128:$dst), (iPTR 0))),
RC:$src))))), RC:$src))))),
(!cast<Instruction>(OpcPrefix#rr_Int) VT:$dst, (!cast<I>(OpcPrefix#rr_Int) VT:$dst,
(COPY_TO_REGCLASS RC:$src, VR128))>; (COPY_TO_REGCLASS RC:$src, VR128))>;
// vector math op with insert via movss/movsd // vector math op with insert via movss/movsd
def : Pat<(VT (Move (VT VR128:$dst), def : Pat<(VT (Move (VT VR128:$dst),
(Op (VT VR128:$dst), (VT VR128:$src)))), (Op (VT VR128:$dst), (VT VR128:$src)))),
(!cast<Instruction>(OpcPrefix#rr_Int) VT:$dst, VT:$src)>; (!cast<I>(OpcPrefix#rr_Int) VT:$dst, VT:$src)>;
} }
// Repeat for AVX versions of the instructions. // Repeat for AVX versions of the instructions.
@ -2662,13 +2662,13 @@ multiclass scalar_math_patterns<SDNode Op, string OpcPrefix, SDNode Move,
def : Pat<(VT (Move (VT VR128:$dst), (VT (scalar_to_vector def : Pat<(VT (Move (VT VR128:$dst), (VT (scalar_to_vector
(Op (EltTy (extractelt (VT VR128:$dst), (iPTR 0))), (Op (EltTy (extractelt (VT VR128:$dst), (iPTR 0))),
RC:$src))))), RC:$src))))),
(!cast<Instruction>("V"#OpcPrefix#rr_Int) VT:$dst, (!cast<I>("V"#OpcPrefix#rr_Int) VT:$dst,
(COPY_TO_REGCLASS RC:$src, VR128))>; (COPY_TO_REGCLASS RC:$src, VR128))>;
// vector math op with insert via movss/movsd // vector math op with insert via movss/movsd
def : Pat<(VT (Move (VT VR128:$dst), def : Pat<(VT (Move (VT VR128:$dst),
(Op (VT VR128:$dst), (VT VR128:$src)))), (Op (VT VR128:$dst), (VT VR128:$src)))),
(!cast<Instruction>("V"#OpcPrefix#rr_Int) VT:$dst, VT:$src)>; (!cast<I>("V"#OpcPrefix#rr_Int) VT:$dst, VT:$src)>;
} }
} }
@ -2927,14 +2927,14 @@ multiclass scalar_unary_math_patterns<SDNode OpNode, string OpcPrefix, SDNode Mo
let Predicates = [BasePredicate] in { let Predicates = [BasePredicate] in {
def : Pat<(VT (Move VT:$dst, (scalar_to_vector def : Pat<(VT (Move VT:$dst, (scalar_to_vector
(OpNode (extractelt VT:$src, 0))))), (OpNode (extractelt VT:$src, 0))))),
(!cast<Instruction>(OpcPrefix#r_Int) VT:$dst, VT:$src)>; (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
} }
// Repeat for AVX versions of the instructions. // Repeat for AVX versions of the instructions.
let Predicates = [UseAVX] in { let Predicates = [HasAVX] in {
def : Pat<(VT (Move VT:$dst, (scalar_to_vector def : Pat<(VT (Move VT:$dst, (scalar_to_vector
(OpNode (extractelt VT:$src, 0))))), (OpNode (extractelt VT:$src, 0))))),
(!cast<Instruction>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>; (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
} }
} }
@ -2944,14 +2944,14 @@ multiclass scalar_unary_math_imm_patterns<SDNode OpNode, string OpcPrefix, SDNod
let Predicates = [BasePredicate] in { let Predicates = [BasePredicate] in {
def : Pat<(VT (Move VT:$dst, (scalar_to_vector def : Pat<(VT (Move VT:$dst, (scalar_to_vector
(OpNode (extractelt VT:$src, 0))))), (OpNode (extractelt VT:$src, 0))))),
(!cast<Instruction>(OpcPrefix#r_Int) VT:$dst, VT:$src, (i32 ImmV))>; (!cast<Ii8>(OpcPrefix#r_Int) VT:$dst, VT:$src, (i32 ImmV))>;
} }
// Repeat for AVX versions of the instructions. // Repeat for AVX versions of the instructions.
let Predicates = [UseAVX] in { let Predicates = [HasAVX] in {
def : Pat<(VT (Move VT:$dst, (scalar_to_vector def : Pat<(VT (Move VT:$dst, (scalar_to_vector
(OpNode (extractelt VT:$src, 0))))), (OpNode (extractelt VT:$src, 0))))),
(!cast<Instruction>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src, (i32 ImmV))>; (!cast<Ii8>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src, (i32 ImmV))>;
} }
} }
@ -2963,13 +2963,13 @@ multiclass scalar_unary_math_intr_patterns<Intrinsic Intr, string OpcPrefix,
Predicate BasePredicate> { Predicate BasePredicate> {
let Predicates = [BasePredicate] in { let Predicates = [BasePredicate] in {
def : Pat<(VT (Move VT:$dst, (Intr VT:$src))), def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
(!cast<Instruction>(OpcPrefix#r_Int) VT:$dst, VT:$src)>; (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
} }
// Repeat for AVX versions of the instructions. // Repeat for AVX versions of the instructions.
let Predicates = [HasAVX] in { let Predicates = [HasAVX] in {
def : Pat<(VT (Move VT:$dst, (Intr VT:$src))), def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
(!cast<Instruction>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>; (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
} }
} }

13
test/CodeGen/X86/sse-intrinsics-fast-isel.ll
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@ -2558,15 +2558,10 @@ define <4 x float> @test_mm_sqrt_ss(<4 x float> %a0) {
; SSE-NEXT: sqrtss %xmm0, %xmm0 # encoding: [0xf3,0x0f,0x51,0xc0] ; SSE-NEXT: sqrtss %xmm0, %xmm0 # encoding: [0xf3,0x0f,0x51,0xc0]
; SSE-NEXT: ret{{[l|q]}} # encoding: [0xc3] ; SSE-NEXT: ret{{[l|q]}} # encoding: [0xc3]
; ;
; AVX1-LABEL: test_mm_sqrt_ss: ; AVX-LABEL: test_mm_sqrt_ss:
; AVX1: # %bb.0: ; AVX: # %bb.0:
; AVX1-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xfa,0x51,0xc0] ; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xfa,0x51,0xc0]
; AVX1-NEXT: ret{{[l|q]}} # encoding: [0xc3] ; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3]
;
; AVX512-LABEL: test_mm_sqrt_ss:
; AVX512: # %bb.0:
; AVX512-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x51,0xc0]
; AVX512-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%ext = extractelement <4 x float> %a0, i32 0 %ext = extractelement <4 x float> %a0, i32 0
%sqrt = call float @llvm.sqrt.f32(float %ext) %sqrt = call float @llvm.sqrt.f32(float %ext)
%ins = insertelement <4 x float> %a0, float %sqrt, i32 0 %ins = insertelement <4 x float> %a0, float %sqrt, i32 0

13
test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll
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@ -34,15 +34,10 @@ define <4 x float> @test_x86_sse_sqrt_ss(<4 x float> %a0) {
; SSE-NEXT: sqrtss %xmm0, %xmm0 ## encoding: [0xf3,0x0f,0x51,0xc0] ; SSE-NEXT: sqrtss %xmm0, %xmm0 ## encoding: [0xf3,0x0f,0x51,0xc0]
; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3] ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
; ;
; AVX1-LABEL: test_x86_sse_sqrt_ss: ; AVX-LABEL: test_x86_sse_sqrt_ss:
; AVX1: ## %bb.0: ; AVX: ## %bb.0:
; AVX1-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x51,0xc0] ; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x51,0xc0]
; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3] ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512-LABEL: test_x86_sse_sqrt_ss:
; AVX512: ## %bb.0:
; AVX512-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x51,0xc0]
; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1] %res = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
ret <4 x float> %res ret <4 x float> %res
} }

13
test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
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@ -4896,15 +4896,10 @@ define <2 x double> @test_mm_sqrt_sd(<2 x double> %a0, <2 x double> %a1) nounwin
; SSE-NEXT: movapd %xmm1, %xmm0 # encoding: [0x66,0x0f,0x28,0xc1] ; SSE-NEXT: movapd %xmm1, %xmm0 # encoding: [0x66,0x0f,0x28,0xc1]
; SSE-NEXT: ret{{[l|q]}} # encoding: [0xc3] ; SSE-NEXT: ret{{[l|q]}} # encoding: [0xc3]
; ;
; AVX1-LABEL: test_mm_sqrt_sd: ; AVX-LABEL: test_mm_sqrt_sd:
; AVX1: # %bb.0: ; AVX: # %bb.0:
; AVX1-NEXT: vsqrtsd %xmm0, %xmm1, %xmm0 # encoding: [0xc5,0xf3,0x51,0xc0] ; AVX-NEXT: vsqrtsd %xmm0, %xmm1, %xmm0 # encoding: [0xc5,0xf3,0x51,0xc0]
; AVX1-NEXT: ret{{[l|q]}} # encoding: [0xc3] ; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3]
;
; AVX512-LABEL: test_mm_sqrt_sd:
; AVX512: # %bb.0:
; AVX512-NEXT: vsqrtsd %xmm0, %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf3,0x51,0xc0]
; AVX512-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%ext = extractelement <2 x double> %a0, i32 0 %ext = extractelement <2 x double> %a0, i32 0
%sqrt = call double @llvm.sqrt.f64(double %ext) %sqrt = call double @llvm.sqrt.f64(double %ext)
%ins = insertelement <2 x double> %a1, double %sqrt, i32 0 %ins = insertelement <2 x double> %a1, double %sqrt, i32 0

17
test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
View File

@ -34,15 +34,10 @@ define <2 x double> @test_x86_sse2_sqrt_sd(<2 x double> %a0) {
; SSE-NEXT: sqrtsd %xmm0, %xmm0 ## encoding: [0xf2,0x0f,0x51,0xc0] ; SSE-NEXT: sqrtsd %xmm0, %xmm0 ## encoding: [0xf2,0x0f,0x51,0xc0]
; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3] ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
; ;
; AVX1-LABEL: test_x86_sse2_sqrt_sd: ; AVX-LABEL: test_x86_sse2_sqrt_sd:
; AVX1: ## %bb.0: ; AVX: ## %bb.0:
; AVX1-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x51,0xc0] ; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x51,0xc0]
; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3] ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512-LABEL: test_x86_sse2_sqrt_sd:
; AVX512: ## %bb.0:
; AVX512-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x51,0xc0]
; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a0) ; <<2 x double>> [#uses=1] %res = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a0) ; <<2 x double>> [#uses=1]
ret <2 x double> %res ret <2 x double> %res
} }
@ -68,7 +63,7 @@ define <2 x double> @test_x86_sse2_sqrt_sd_vec_load(<2 x double>* %a0) {
; X86-AVX512: ## %bb.0: ; X86-AVX512: ## %bb.0:
; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04] ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-AVX512-NEXT: vmovapd (%eax), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0x00] ; X86-AVX512-NEXT: vmovapd (%eax), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0x00]
; X86-AVX512-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x51,0xc0] ; X86-AVX512-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x51,0xc0]
; X86-AVX512-NEXT: retl ## encoding: [0xc3] ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
; ;
; X64-SSE-LABEL: test_x86_sse2_sqrt_sd_vec_load: ; X64-SSE-LABEL: test_x86_sse2_sqrt_sd_vec_load:
@ -86,7 +81,7 @@ define <2 x double> @test_x86_sse2_sqrt_sd_vec_load(<2 x double>* %a0) {
; X64-AVX512-LABEL: test_x86_sse2_sqrt_sd_vec_load: ; X64-AVX512-LABEL: test_x86_sse2_sqrt_sd_vec_load:
; X64-AVX512: ## %bb.0: ; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vmovapd (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0x07] ; X64-AVX512-NEXT: vmovapd (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0x07]
; X64-AVX512-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x51,0xc0] ; X64-AVX512-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x51,0xc0]
; X64-AVX512-NEXT: retq ## encoding: [0xc3] ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
%a1 = load <2 x double>, <2 x double>* %a0, align 16 %a1 = load <2 x double>, <2 x double>* %a0, align 16
%res = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a1) ; <<2 x double>> [#uses=1] %res = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a1) ; <<2 x double>> [#uses=1]