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[X86] Add hasSideEffects=0 to some instructions.

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llvm-svn: 280782
This commit is contained in:
Craig Topper 2016-09-07 04:46:15 +00:00
parent a231c68058
commit 6b7eb97ac7
2 changed files with 5 additions and 3 deletions
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1
lib/Target/X86/X86InstrAVX512.td
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@ -5619,6 +5619,7 @@ let Predicates = [HasAVX512] in {
def rr : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src), def rr : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
!strconcat(asm,"\t{$src, $dst|$dst, $src}"), !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
[(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX; [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
let hasSideEffects = 0 in
def rb : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src), def rb : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
!strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"), !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
[]>, EVEX, EVEX_B; []>, EVEX, EVEX_B;

7
lib/Target/X86/X86InstrSSE.td
View File

@ -3880,13 +3880,14 @@ def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
} }
let SchedRW = [WriteMove] in { let SchedRW = [WriteMove] in {
let hasSideEffects = 0 in let hasSideEffects = 0 in {
def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>; "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"movdqu\t{$src, $dst|$dst, $src}", "movdqu\t{$src, $dst|$dst, $src}",
[], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>; [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
}
// For Disassembler // For Disassembler
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
@ -6415,7 +6416,7 @@ let ExeDomain = GenericDomain in {
[]>, Sched<[WriteFAdd]>; []>, Sched<[WriteFAdd]>;
// Operation, mem. // Operation, mem.
let mayLoad = 1 in let mayLoad = 1, hasSideEffects = 0 in
def SSm : SS4AIi8<opcss, MRMSrcMem, def SSm : SS4AIi8<opcss, MRMSrcMem,
(outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, i32u8imm:$src3), (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, i32u8imm:$src3),
!if(Is2Addr, !if(Is2Addr,
@ -6462,7 +6463,7 @@ let ExeDomain = GenericDomain in {
[]>, Sched<[WriteFAdd]>; []>, Sched<[WriteFAdd]>;
// Operation, mem. // Operation, mem.
let mayLoad = 1 in let mayLoad = 1, hasSideEffects = 0 in
def SDm : SS4AIi8<opcsd, MRMSrcMem, def SDm : SS4AIi8<opcsd, MRMSrcMem,
(outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, i32u8imm:$src3), (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, i32u8imm:$src3),
!if(Is2Addr, !if(Is2Addr,