1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 11:02:59 +02:00

[Hexagon] Handle more types of immediate operands in expand-condsets

llvm-svn: 305943
This commit is contained in:
Krzysztof Parzyszek 2017-06-21 19:21:30 +00:00
parent a033cc7429
commit 6b8f89e421
2 changed files with 35 additions and 2 deletions

View File

@ -567,8 +567,19 @@ unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
}
llvm_unreachable("Invalid register operand");
}
if (SO.isImm() || SO.isFPImm())
return IfTrue ? C2_cmoveit : C2_cmoveif;
switch (SO.getType()) {
case MachineOperand::MO_Immediate:
case MachineOperand::MO_FPImmediate:
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_TargetIndex:
case MachineOperand::MO_JumpTableIndex:
case MachineOperand::MO_ExternalSymbol:
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_BlockAddress:
return IfTrue ? C2_cmoveit : C2_cmoveif;
default:
break;
}
llvm_unreachable("Unexpected source operand");
}

View File

@ -0,0 +1,22 @@
# RUN: llc -march=hexagon -run-pass expand-condsets %s -o - | FileCheck %s
# Check that we can expand a mux with a global as an immediate operand.
# CHECK: C2_cmoveif undef %0, @G
--- |
@G = global i32 0, align 4
define void @fred() { ret void }
...
---
name: fred
tracksRegLiveness: true
registers:
- { id: 0, class: predregs }
- { id: 1, class: intregs }
body: |
bb.1:
%1 = IMPLICIT_DEF
%1 = C2_muxir undef %0, %1, @G
%r0 = COPY %1
...