RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Code Issues Projects Releases Wiki Activity

move sldt, imul, and movabsq aliases from c++ to .td file.

Browse Source 
llvm-svn: 118347
This commit is contained in:
Chris Lattner 2010-11-06 18:44:26 +00:00
parent 1beb2b3fc5
commit 6b905e3a10
2 changed files with 18 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -752,15 +752,6 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
if (getLexer().is(AsmToken::EndOfStatement))
Parser.Lex(); // Consume the EndOfStatement
// Hack to allow 'movq <largeimm>, <reg>' as an alias for movabsq.
if ((Name == "movq" || Name == "mov") && Operands.size() == 3 &&
static_cast<X86Operand*>(Operands[2])->isReg() &&
static_cast<X86Operand*>(Operands[1])->isImm() &&
!static_cast<X86Operand*>(Operands[1])->isImmSExti64i32()) {
delete Operands[0];
Operands[0] = X86Operand::CreateToken("movabsq", NameLoc);
}
// FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
// "shift <op>".
if ((Name.startswith("shr") || Name.startswith("sar") ||
@ -858,26 +849,6 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
Operands.erase(Operands.begin() + 1);
}
// FIXME: Hack to handle "imul <imm>, B" which is an alias for "imul <imm>, B,
// B".
if (Name.startswith("imul") && Operands.size() == 3 &&
static_cast<X86Operand*>(Operands[1])->isImm() &&
static_cast<X86Operand*>(Operands.back())->isReg()) {
X86Operand *Op = static_cast<X86Operand*>(Operands.back());
Operands.push_back(X86Operand::CreateReg(Op->getReg(), Op->getStartLoc(),
Op->getEndLoc()));
}
// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
// errors, since its encoding is the most compact.
if (Name == "sldt" && Operands.size() == 2 &&
static_cast<X86Operand*>(Operands[1])->isMem()) {
delete Operands[0];
Operands[0] = X86Operand::CreateToken("sldtw", NameLoc);
}
// The assembler accepts these instructions with no operand as a synonym for
// an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)".
if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" ||

18
lib/Target/X86/X86InstrInfo.td
View File

@ -1380,6 +1380,15 @@ def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
// "imul <imm>, B" is an alias for "imul <imm>, B, B".
def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
@ -1389,6 +1398,9 @@ def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
// Match 'movq <largeimm>, <reg>' as an alias for movabsq.
def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
// movsd with no operands (as opposed to the SSE scalar move of a double) is an
// alias for movsl. (as in rep; movsd)
def : InstAlias<"movsd", (MOVSD)>;
@ -1411,6 +1423,12 @@ def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src)>;
def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src)>;
// Note: No GR32->GR64 movzx form.
// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
// errors, since its encoding is the most compact.
def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;