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Hexagon: Add patterns for zero extended loads from i1->i64.
llvm-svn: 176689
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@ -2875,6 +2875,18 @@ def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
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s11_0ExtPred:$offset)))>,
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Requires<[NoV4T]>;
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// i1 -> i64
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def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
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(i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
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Requires<[NoV4T]>;
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let AddedComplexity = 20 in
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def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
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s11_0ExtPred:$offset))),
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(i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
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s11_0ExtPred:$offset)))>,
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Requires<[NoV4T]>;
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// i16 -> i64
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def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
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(i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>,
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@ -940,6 +940,18 @@ def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
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s11_0ExtPred:$offset)))>,
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Requires<[HasV4T]>;
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// zext i1->i64
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def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
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(i64 (COMBINE_Ir_V4 0, (LDriub ADDRriS11_0:$src1)))>,
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Requires<[HasV4T]>;
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let AddedComplexity = 20 in
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def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
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s11_0ExtPred:$offset))),
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(i64 (COMBINE_Ir_V4 0, (LDriub_indexed IntRegs:$src1,
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s11_0ExtPred:$offset)))>,
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Requires<[HasV4T]>;
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// zext i16->i64
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def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
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(i64 (COMBINE_Ir_V4 0, (LDriuh ADDRriS11_1:$src1)))>,
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25
test/CodeGen/Hexagon/zextloadi1.ll
Normal file
25
test/CodeGen/Hexagon/zextloadi1.ll
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@ -0,0 +1,25 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; CHECK: r{{[0-9]+}} = ##i129_l+16
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; CHECK: r{{[0-9]+}} = ##i129_s+16
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; CHECK: memd(##i129_s) = r{{[0-9]+:[0-9]+}}
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; CHECK: r{{[0-9]+}} = ##i65_l+8
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; CHECK: r{{[0-9]+}} = ##i65_s+8
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; CHECK: memd(##i65_s) = r{{[0-9]+:[0-9]+}}
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@i65_l = external global i65
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@i65_s = external global i65
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@i129_l = external global i129
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@i129_s = external global i129
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define void @i129_ls() nounwind {
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%tmp = load i129* @i129_l
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store i129 %tmp, i129* @i129_s
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ret void
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}
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define void @i65_ls() nounwind {
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%tmp = load i65* @i65_l
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store i65 %tmp, i65* @i65_s
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ret void
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}
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