RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 18:54:02 +01:00
Code Issues Projects Releases Wiki Activity

GlobalISel: fix comparison order for G_FCMP

Browse Source 
As with G_ICMP we'd written the CSET instructions backwards.

llvm-svn: 292285
This commit is contained in:
Tim Northover 2017-01-17 23:04:01 +00:00
parent c4d9f99729
commit 6bb5c42da0
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/AArch64/AArch64InstructionSelector.cpp
View File

@ -1134,7 +1134,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
.addDef(Def1Reg)
.addUse(AArch64::WZR)
.addUse(AArch64::WZR)
.addImm(CC1);
.addImm(getInvertedCondCode(CC1));
if (CC2 != AArch64CC::AL) {
unsigned Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
@ -1143,7 +1143,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
.addDef(Def2Reg)
.addUse(AArch64::WZR)
.addUse(AArch64::WZR)
.addImm(CC2);
.addImm(getInvertedCondCode(CC2));
MachineInstr &OrMI =
*BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ORRWrr))
.addDef(DefReg)

6
test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
View File

@ -2879,12 +2879,12 @@ registers:
# CHECK: body:
# CHECK: FCMPSrr %0, %0, implicit-def %nzcv
# CHECK: [[TST_MI:%[0-9]+]] = CSINCWr %wzr, %wzr, 4, implicit %nzcv
# CHECK: [[TST_GT:%[0-9]+]] = CSINCWr %wzr, %wzr, 12, implicit %nzcv
# CHECK: [[TST_MI:%[0-9]+]] = CSINCWr %wzr, %wzr, 5, implicit %nzcv
# CHECK: [[TST_GT:%[0-9]+]] = CSINCWr %wzr, %wzr, 13, implicit %nzcv
# CHECK: %1 = ORRWrr [[TST_MI]], [[TST_GT]]
# CHECK: FCMPDrr %2, %2, implicit-def %nzcv
# CHECK: %3 = CSINCWr %wzr, %wzr, 5, implicit %nzcv
# CHECK: %3 = CSINCWr %wzr, %wzr, 4, implicit %nzcv
body: |
bb.0: