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[mips] 80-column.
llvm-svn: 204252
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@ -42,14 +42,18 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
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const MCSubtargetInfo &STI,
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MCContext &Ctx);
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MCAsmBackend *createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
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const MCRegisterInfo &MRI, StringRef TT,
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StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
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const MCRegisterInfo &MRI, StringRef TT,
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StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
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const MCRegisterInfo &MRI, StringRef TT,
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StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
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const MCRegisterInfo &MRI, StringRef TT,
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StringRef CPU);
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MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS,
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uint8_t OSABI,
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