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Mark masked.{store,scatter,compressstore} intrinsics as write-only

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This commit is contained in:
Krzysztof Parzyszek 2020-09-09 17:27:04 -05:00
parent 4b96a7282b
commit 6bc3ff08f3
3 changed files with 33 additions and 33 deletions
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62
include/llvm/IR/Intrinsics.td
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@ -1349,42 +1349,42 @@ def int_get_active_lane_mask:
//===-------------------------- Masked Intrinsics -------------------------===//
//
def int_masked_store : Intrinsic<[], [llvm_anyvector_ty,
LLVMAnyPointerType<LLVMMatchType<0>>,
llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[IntrArgMemOnly, IntrWillReturn, ImmArg<ArgIndex<2>>]>;
def int_masked_load:
Intrinsic<[llvm_anyvector_ty],
[LLVMAnyPointerType<LLVMMatchType<0>>, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>],
[IntrReadMem, IntrArgMemOnly, IntrWillReturn, ImmArg<ArgIndex<1>>]>;
def int_masked_load : Intrinsic<[llvm_anyvector_ty],
[LLVMAnyPointerType<LLVMMatchType<0>>, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>],
[IntrReadMem, IntrArgMemOnly, IntrWillReturn,
ImmArg<ArgIndex<1>>]>;
def int_masked_store:
Intrinsic<[],
[llvm_anyvector_ty, LLVMAnyPointerType<LLVMMatchType<0>>,
llvm_i32_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[IntrWriteMem, IntrArgMemOnly, IntrWillReturn,
ImmArg<ArgIndex<2>>]>;
def int_masked_gather: Intrinsic<[llvm_anyvector_ty],
[LLVMVectorOfAnyPointersToElt<0>, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<0>],
[IntrReadMem, IntrWillReturn,
ImmArg<ArgIndex<1>>]>;
def int_masked_gather:
Intrinsic<[llvm_anyvector_ty],
[LLVMVectorOfAnyPointersToElt<0>, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>],
[IntrReadMem, IntrWillReturn, ImmArg<ArgIndex<1>>]>;
def int_masked_scatter: Intrinsic<[],
[llvm_anyvector_ty,
LLVMVectorOfAnyPointersToElt<0>, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[IntrWillReturn, ImmArg<ArgIndex<2>>]>;
def int_masked_scatter:
Intrinsic<[],
[llvm_anyvector_ty, LLVMVectorOfAnyPointersToElt<0>, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[IntrWriteMem, IntrWillReturn, ImmArg<ArgIndex<2>>]>;
def int_masked_expandload: Intrinsic<[llvm_anyvector_ty],
[LLVMPointerToElt<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<0>],
[IntrReadMem, IntrWillReturn]>;
def int_masked_expandload:
Intrinsic<[llvm_anyvector_ty],
[LLVMPointerToElt<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<0>],
[IntrReadMem, IntrWillReturn]>;
def int_masked_compressstore: Intrinsic<[],
[llvm_anyvector_ty,
LLVMPointerToElt<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[IntrArgMemOnly, IntrWillReturn]>;
def int_masked_compressstore:
Intrinsic<[],
[llvm_anyvector_ty, LLVMPointerToElt<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[IntrWriteMem, IntrArgMemOnly, IntrWillReturn]>;
// Test whether a pointer is associated with a type metadata identifier.
def int_type_test : Intrinsic<[llvm_i1_ty], [llvm_ptr_ty, llvm_metadata_ty],

2
test/Analysis/BasicAA/intrinsics.ll
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@ -23,5 +23,5 @@ declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32, <8 x i1>, <8
declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>) nounwind
; CHECK: attributes #0 = { argmemonly nounwind readonly willreturn }
; CHECK: attributes #1 = { argmemonly nounwind willreturn }
; CHECK: attributes #1 = { argmemonly nounwind willreturn writeonly }
; CHECK: attributes [[ATTR]] = { nounwind }

2
test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll
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@ -23,7 +23,7 @@ declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32, <8 x i1>, <8
declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>) nounwind
; CHECK: attributes #0 = { argmemonly nounwind readonly willreturn }
; CHECK: attributes #1 = { argmemonly nounwind willreturn }
; CHECK: attributes #1 = { argmemonly nounwind willreturn writeonly }
; CHECK: attributes [[NUW]] = { nounwind }
!0 = !{!"tbaa root"}