mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 03:33:20 +01:00
Rename Interval class to LiveInterval to avoid conflicting with the already
existing llvm::Interval class. Patch contributed by Vladimir Prus! http://mail.cs.uiuc.edu/pipermail/llvmbugs/2004-June/000710.html llvm-svn: 14281
This commit is contained in:
parent
3a8e3bce6c
commit
6be1c456a8
@ -136,7 +136,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
|
||||
if (tii.isMoveInstr(*mii, srcReg, dstReg) &&
|
||||
rep(srcReg) == rep(dstReg)) {
|
||||
// remove from def list
|
||||
Interval& interval = getOrCreateInterval(rep(dstReg));
|
||||
LiveInterval& interval = getOrCreateInterval(rep(dstReg));
|
||||
// remove index -> MachineInstr and
|
||||
// MachineInstr -> index mappings
|
||||
Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii);
|
||||
@ -170,7 +170,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
|
||||
intervals_.sort();
|
||||
DEBUG(std::cerr << "********** INTERVALS **********\n");
|
||||
DEBUG(std::copy(intervals_.begin(), intervals_.end(),
|
||||
std::ostream_iterator<Interval>(std::cerr, "\n")));
|
||||
std::ostream_iterator<LiveInterval>(std::cerr, "\n")));
|
||||
DEBUG(std::cerr << "********** MACHINEINSTRS **********\n");
|
||||
DEBUG(
|
||||
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
|
||||
@ -186,11 +186,12 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
|
||||
return true;
|
||||
}
|
||||
|
||||
std::vector<Interval*> LiveIntervals::addIntervalsForSpills(const Interval& li,
|
||||
VirtRegMap& vrm,
|
||||
int slot)
|
||||
std::vector<LiveInterval*> LiveIntervals::addIntervalsForSpills(
|
||||
const LiveInterval& li,
|
||||
VirtRegMap& vrm,
|
||||
int slot)
|
||||
{
|
||||
std::vector<Interval*> added;
|
||||
std::vector<LiveInterval*> added;
|
||||
|
||||
assert(li.weight != HUGE_VAL &&
|
||||
"attempt to spill already spilled interval!");
|
||||
@ -200,7 +201,7 @@ std::vector<Interval*> LiveIntervals::addIntervalsForSpills(const Interval& li,
|
||||
|
||||
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
|
||||
|
||||
for (Interval::Ranges::const_iterator
|
||||
for (LiveInterval::Ranges::const_iterator
|
||||
i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
|
||||
unsigned index = getBaseIndex(i->first);
|
||||
unsigned end = getBaseIndex(i->second-1) + InstrSlots::NUM;
|
||||
@ -250,7 +251,7 @@ std::vector<Interval*> LiveIntervals::addIntervalsForSpills(const Interval& li,
|
||||
mi->SetMachineOperandReg(i, nReg);
|
||||
vrm.grow();
|
||||
vrm.assignVirt2StackSlot(nReg, slot);
|
||||
Interval& nI = getOrCreateInterval(nReg);
|
||||
LiveInterval& nI = getOrCreateInterval(nReg);
|
||||
assert(nI.empty());
|
||||
// the spill weight is now infinity as it
|
||||
// cannot be spilled again
|
||||
@ -280,7 +281,7 @@ void LiveIntervals::printRegName(unsigned reg) const
|
||||
|
||||
void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb,
|
||||
MachineBasicBlock::iterator mi,
|
||||
Interval& interval)
|
||||
LiveInterval& interval)
|
||||
{
|
||||
DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
|
||||
LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
|
||||
@ -334,7 +335,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb,
|
||||
|
||||
void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock* mbb,
|
||||
MachineBasicBlock::iterator mi,
|
||||
Interval& interval)
|
||||
LiveInterval& interval)
|
||||
{
|
||||
DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
|
||||
typedef LiveVariables::killed_iterator KillIter;
|
||||
@ -536,8 +537,8 @@ void LiveIntervals::joinIntervals()
|
||||
}
|
||||
}
|
||||
|
||||
bool LiveIntervals::overlapsAliases(const Interval& lhs,
|
||||
const Interval& rhs) const
|
||||
bool LiveIntervals::overlapsAliases(const LiveInterval& lhs,
|
||||
const LiveInterval& rhs) const
|
||||
{
|
||||
assert(MRegisterInfo::isPhysicalRegister(lhs.reg) &&
|
||||
"first interval must describe a physical register");
|
||||
@ -552,24 +553,24 @@ bool LiveIntervals::overlapsAliases(const Interval& lhs,
|
||||
return false;
|
||||
}
|
||||
|
||||
Interval& LiveIntervals::getOrCreateInterval(unsigned reg)
|
||||
LiveInterval& LiveIntervals::getOrCreateInterval(unsigned reg)
|
||||
{
|
||||
Reg2IntervalMap::iterator r2iit = r2iMap_.lower_bound(reg);
|
||||
if (r2iit == r2iMap_.end() || r2iit->first != reg) {
|
||||
intervals_.push_back(Interval(reg));
|
||||
intervals_.push_back(LiveInterval(reg));
|
||||
r2iit = r2iMap_.insert(r2iit, std::make_pair(reg, --intervals_.end()));
|
||||
}
|
||||
|
||||
return *r2iit->second;
|
||||
}
|
||||
|
||||
Interval::Interval(unsigned r)
|
||||
LiveInterval::LiveInterval(unsigned r)
|
||||
: reg(r),
|
||||
weight((MRegisterInfo::isPhysicalRegister(r) ? HUGE_VAL : 0.0F))
|
||||
{
|
||||
}
|
||||
|
||||
bool Interval::spilled() const
|
||||
bool LiveInterval::spilled() const
|
||||
{
|
||||
return (weight == HUGE_VAL &&
|
||||
MRegisterInfo::isVirtualRegister(reg));
|
||||
@ -582,7 +583,7 @@ bool Interval::spilled() const
|
||||
// definition of the variable it represents. This is because slot 1 is
|
||||
// used (def slot) and spans up to slot 3 (store slot).
|
||||
//
|
||||
bool Interval::liveAt(unsigned index) const
|
||||
bool LiveInterval::liveAt(unsigned index) const
|
||||
{
|
||||
Range dummy(index, index+1);
|
||||
Ranges::const_iterator r = std::upper_bound(ranges.begin(),
|
||||
@ -609,7 +610,7 @@ bool Interval::liveAt(unsigned index) const
|
||||
//
|
||||
// A->overlaps(C) should return false since we want to be able to join
|
||||
// A and C.
|
||||
bool Interval::overlaps(const Interval& other) const
|
||||
bool LiveInterval::overlaps(const LiveInterval& other) const
|
||||
{
|
||||
Ranges::const_iterator i = ranges.begin();
|
||||
Ranges::const_iterator ie = ranges.end();
|
||||
@ -647,7 +648,7 @@ bool Interval::overlaps(const Interval& other) const
|
||||
return false;
|
||||
}
|
||||
|
||||
void Interval::addRange(unsigned start, unsigned end)
|
||||
void LiveInterval::addRange(unsigned start, unsigned end)
|
||||
{
|
||||
assert(start < end && "Invalid range to add!");
|
||||
DEBUG(std::cerr << " +[" << start << ',' << end << ")");
|
||||
@ -661,7 +662,7 @@ void Interval::addRange(unsigned start, unsigned end)
|
||||
it = mergeRangesBackward(it);
|
||||
}
|
||||
|
||||
void Interval::join(const Interval& other)
|
||||
void LiveInterval::join(const LiveInterval& other)
|
||||
{
|
||||
DEBUG(std::cerr << "\t\tjoining " << *this << " with " << other << '\n');
|
||||
Ranges::iterator cur = ranges.begin();
|
||||
@ -676,7 +677,8 @@ void Interval::join(const Interval& other)
|
||||
++numJoins;
|
||||
}
|
||||
|
||||
Interval::Ranges::iterator Interval::mergeRangesForward(Ranges::iterator it)
|
||||
LiveInterval::Ranges::iterator LiveInterval::
|
||||
mergeRangesForward(Ranges::iterator it)
|
||||
{
|
||||
Ranges::iterator n;
|
||||
while ((n = next(it)) != ranges.end()) {
|
||||
@ -688,7 +690,8 @@ Interval::Ranges::iterator Interval::mergeRangesForward(Ranges::iterator it)
|
||||
return it;
|
||||
}
|
||||
|
||||
Interval::Ranges::iterator Interval::mergeRangesBackward(Ranges::iterator it)
|
||||
LiveInterval::Ranges::iterator LiveInterval::
|
||||
mergeRangesBackward(Ranges::iterator it)
|
||||
{
|
||||
while (it != ranges.begin()) {
|
||||
Ranges::iterator p = prior(it);
|
||||
@ -703,14 +706,14 @@ Interval::Ranges::iterator Interval::mergeRangesBackward(Ranges::iterator it)
|
||||
return it;
|
||||
}
|
||||
|
||||
std::ostream& llvm::operator<<(std::ostream& os, const Interval& li)
|
||||
std::ostream& llvm::operator<<(std::ostream& os, const LiveInterval& li)
|
||||
{
|
||||
os << "%reg" << li.reg << ',' << li.weight;
|
||||
if (li.empty())
|
||||
return os << "EMPTY";
|
||||
|
||||
os << " = ";
|
||||
for (Interval::Ranges::const_iterator
|
||||
for (LiveInterval::Ranges::const_iterator
|
||||
i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
|
||||
os << "[" << i->first << "," << i->second << ")";
|
||||
}
|
||||
|
@ -30,7 +30,7 @@ namespace llvm {
|
||||
class MRegisterInfo;
|
||||
class VirtRegMap;
|
||||
|
||||
struct Interval {
|
||||
struct LiveInterval {
|
||||
typedef std::pair<unsigned, unsigned> Range;
|
||||
typedef std::vector<Range> Ranges;
|
||||
unsigned reg; // the register of this interval
|
||||
@ -38,7 +38,7 @@ namespace llvm {
|
||||
// (number of uses *10^loopDepth)
|
||||
Ranges ranges; // the ranges in which this register is live
|
||||
|
||||
explicit Interval(unsigned r);
|
||||
explicit LiveInterval(unsigned r);
|
||||
|
||||
bool empty() const { return ranges.empty(); }
|
||||
|
||||
@ -60,17 +60,17 @@ namespace llvm {
|
||||
|
||||
bool liveAt(unsigned index) const;
|
||||
|
||||
bool overlaps(const Interval& other) const;
|
||||
bool overlaps(const LiveInterval& other) const;
|
||||
|
||||
void addRange(unsigned start, unsigned end);
|
||||
|
||||
void join(const Interval& other);
|
||||
void join(const LiveInterval& other);
|
||||
|
||||
bool operator<(const Interval& other) const {
|
||||
bool operator<(const LiveInterval& other) const {
|
||||
return start() < other.start();
|
||||
}
|
||||
|
||||
bool operator==(const Interval& other) const {
|
||||
bool operator==(const LiveInterval& other) const {
|
||||
return reg == other.reg;
|
||||
}
|
||||
|
||||
@ -79,12 +79,12 @@ namespace llvm {
|
||||
Ranges::iterator mergeRangesBackward(Ranges::iterator it);
|
||||
};
|
||||
|
||||
std::ostream& operator<<(std::ostream& os, const Interval& li);
|
||||
std::ostream& operator<<(std::ostream& os, const LiveInterval& li);
|
||||
|
||||
class LiveIntervals : public MachineFunctionPass
|
||||
{
|
||||
public:
|
||||
typedef std::list<Interval> Intervals;
|
||||
typedef std::list<LiveInterval> Intervals;
|
||||
|
||||
private:
|
||||
MachineFunction* mf_;
|
||||
@ -148,7 +148,7 @@ namespace llvm {
|
||||
/// runOnMachineFunction - pass entry point
|
||||
virtual bool runOnMachineFunction(MachineFunction&);
|
||||
|
||||
Interval& getInterval(unsigned reg) {
|
||||
LiveInterval& getInterval(unsigned reg) {
|
||||
assert(r2iMap_.count(reg)&& "Interval does not exist for register");
|
||||
return *r2iMap_.find(reg)->second;
|
||||
}
|
||||
@ -162,9 +162,9 @@ namespace llvm {
|
||||
|
||||
Intervals& getIntervals() { return intervals_; }
|
||||
|
||||
std::vector<Interval*> addIntervalsForSpills(const Interval& i,
|
||||
VirtRegMap& vrm,
|
||||
int slot);
|
||||
std::vector<LiveInterval*> addIntervalsForSpills(const LiveInterval& i,
|
||||
VirtRegMap& vrm,
|
||||
int slot);
|
||||
|
||||
private:
|
||||
/// computeIntervals - compute live intervals
|
||||
@ -184,18 +184,19 @@ namespace llvm {
|
||||
/// register def
|
||||
void handleVirtualRegisterDef(MachineBasicBlock* mbb,
|
||||
MachineBasicBlock::iterator mi,
|
||||
Interval& interval);
|
||||
LiveInterval& interval);
|
||||
|
||||
/// handlePhysicalRegisterDef - update intervals for a
|
||||
/// physical register def
|
||||
void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
|
||||
MachineBasicBlock::iterator mi,
|
||||
Interval& interval);
|
||||
LiveInterval& interval);
|
||||
|
||||
bool overlapsAliases(const Interval& lhs, const Interval& rhs) const;
|
||||
bool overlapsAliases(const LiveInterval& lhs,
|
||||
const LiveInterval& rhs) const;
|
||||
|
||||
|
||||
Interval& getOrCreateInterval(unsigned reg);
|
||||
LiveInterval& getOrCreateInterval(unsigned reg);
|
||||
|
||||
/// rep - returns the representative of this register
|
||||
unsigned rep(unsigned reg);
|
||||
|
@ -39,7 +39,7 @@ namespace {
|
||||
const TargetMachine* tm_;
|
||||
const MRegisterInfo* mri_;
|
||||
LiveIntervals* li_;
|
||||
typedef std::list<Interval*> IntervalPtrs;
|
||||
typedef std::list<LiveInterval*> IntervalPtrs;
|
||||
IntervalPtrs unhandled_, fixed_, active_, inactive_, handled_;
|
||||
|
||||
std::auto_ptr<PhysRegTracker> prt_;
|
||||
@ -374,12 +374,12 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
|
||||
if (cur->weight <= minWeight) {
|
||||
DEBUG(std::cerr << "\t\t\tspilling(c): " << *cur << '\n';);
|
||||
int slot = vrm_->assignVirt2StackSlot(cur->reg);
|
||||
std::vector<Interval*> added =
|
||||
std::vector<LiveInterval*> added =
|
||||
li_->addIntervalsForSpills(*cur, *vrm_, slot);
|
||||
|
||||
// merge added with unhandled
|
||||
std::vector<Interval*>::iterator addedIt = added.begin();
|
||||
std::vector<Interval*>::iterator addedItEnd = added.end();
|
||||
std::vector<LiveInterval*>::iterator addedIt = added.begin();
|
||||
std::vector<LiveInterval*>::iterator addedItEnd = added.end();
|
||||
for (IntervalPtrs::iterator i = unhandled_.begin(), e = unhandled_.end();
|
||||
i != e && addedIt != addedItEnd; ++i) {
|
||||
if ((*i)->start() > (*addedIt)->start())
|
||||
@ -399,7 +399,7 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
|
||||
// otherwise we spill all intervals aliasing the register with
|
||||
// minimum weight, rollback to the interval with the earliest
|
||||
// start point and let the linear scan algorithm run again
|
||||
std::vector<Interval*> added;
|
||||
std::vector<LiveInterval*> added;
|
||||
assert(MRegisterInfo::isPhysicalRegister(minReg) &&
|
||||
"did not choose a register to spill?");
|
||||
std::vector<bool> toSpill(mri_->getNumRegs(), false);
|
||||
@ -418,7 +418,7 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
|
||||
DEBUG(std::cerr << "\t\t\tspilling(a): " << **i << '\n');
|
||||
earliestStart = std::min(earliestStart, (*i)->start());
|
||||
int slot = vrm_->assignVirt2StackSlot((*i)->reg);
|
||||
std::vector<Interval*> newIs =
|
||||
std::vector<LiveInterval*> newIs =
|
||||
li_->addIntervalsForSpills(**i, *vrm_, slot);
|
||||
std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
|
||||
spilled.insert(reg);
|
||||
@ -433,7 +433,7 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
|
||||
DEBUG(std::cerr << "\t\t\tspilling(i): " << **i << '\n');
|
||||
earliestStart = std::min(earliestStart, (*i)->start());
|
||||
int slot = vrm_->assignVirt2StackSlot((*i)->reg);
|
||||
std::vector<Interval*> newIs =
|
||||
std::vector<LiveInterval*> newIs =
|
||||
li_->addIntervalsForSpills(**i, *vrm_, slot);
|
||||
std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
|
||||
spilled.insert(reg);
|
||||
@ -496,10 +496,10 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
|
||||
}
|
||||
}
|
||||
|
||||
std::sort(added.begin(), added.end(), less_ptr<Interval>());
|
||||
std::sort(added.begin(), added.end(), less_ptr<LiveInterval>());
|
||||
// merge added with unhandled
|
||||
std::vector<Interval*>::iterator addedIt = added.begin();
|
||||
std::vector<Interval*>::iterator addedItEnd = added.end();
|
||||
std::vector<LiveInterval*>::iterator addedIt = added.begin();
|
||||
std::vector<LiveInterval*>::iterator addedItEnd = added.end();
|
||||
for (IntervalPtrs::iterator i = unhandled_.begin(), e = unhandled_.end();
|
||||
i != e && addedIt != addedItEnd; ++i) {
|
||||
if ((*i)->start() > (*addedIt)->start())
|
||||
|
Loading…
Reference in New Issue
Block a user