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fix documentation comments; NFC
llvm-svn: 275101
This commit is contained in:
Sanjay Patel
parent
7abab61a0e
commit
6be59af417
@ -878,56 +878,52 @@ namespace ISD {
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SETCC_INVALID // Marker value.
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};
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/// isSignedIntSetCC - Return true if this is a setcc instruction that
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/// performs a signed comparison when used with integer operands.
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/// Return true if this is a setcc instruction that performs a signed
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/// comparison when used with integer operands.
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inline bool isSignedIntSetCC(CondCode Code) {
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return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
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}
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/// isUnsignedIntSetCC - Return true if this is a setcc instruction that
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/// performs an unsigned comparison when used with integer operands.
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/// Return true if this is a setcc instruction that performs an unsigned
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/// comparison when used with integer operands.
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inline bool isUnsignedIntSetCC(CondCode Code) {
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return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
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}
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/// isTrueWhenEqual - Return true if the specified condition returns true if
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/// the two operands to the condition are equal. Note that if one of the two
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/// operands is a NaN, this value is meaningless.
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/// Return true if the specified condition returns true if the two operands to
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/// the condition are equal. Note that if one of the two operands is a NaN,
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/// this value is meaningless.
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inline bool isTrueWhenEqual(CondCode Cond) {
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return ((int)Cond & 1) != 0;
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}
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/// getUnorderedFlavor - This function returns 0 if the condition is always
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/// false if an operand is a NaN, 1 if the condition is always true if the
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/// operand is a NaN, and 2 if the condition is undefined if the operand is a
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/// NaN.
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/// This function returns 0 if the condition is always false if an operand is
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/// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
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/// the condition is undefined if the operand is a NaN.
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inline unsigned getUnorderedFlavor(CondCode Cond) {
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return ((int)Cond >> 3) & 3;
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}
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/// getSetCCInverse - Return the operation corresponding to !(X op Y), where
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/// 'op' is a valid SetCC operation.
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/// Return the operation corresponding to !(X op Y), where 'op' is a valid
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/// SetCC operation.
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CondCode getSetCCInverse(CondCode Operation, bool isInteger);
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/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
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/// when given the operation for (X op Y).
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/// Return the operation corresponding to (Y op X) when given the operation
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/// for (X op Y).
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CondCode getSetCCSwappedOperands(CondCode Operation);
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/// getSetCCOrOperation - Return the result of a logical OR between different
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/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This
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/// function returns SETCC_INVALID if it is not possible to represent the
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/// resultant comparison.
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/// Return the result of a logical OR between different comparisons of
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/// identical values: ((X op1 Y) | (X op2 Y)). This function returns
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/// SETCC_INVALID if it is not possible to represent the resultant comparison.
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CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
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/// getSetCCAndOperation - Return the result of a logical AND between
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/// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
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/// function returns SETCC_INVALID if it is not possible to represent the
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/// resultant comparison.
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/// Return the result of a logical AND between different comparisons of
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/// identical values: ((X op1 Y) & (X op2 Y)). This function returns
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/// SETCC_INVALID if it is not possible to represent the resultant comparison.
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CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
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//===--------------------------------------------------------------------===//
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/// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT
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/// supports.
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/// This enum defines the various converts CONVERT_RNDSAT supports.
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enum CvtCode {
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CVT_FF, /// Float from Float
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CVT_FS, /// Float from Signed
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@ -1235,13 +1235,12 @@ public:
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void dump() const;
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/// Create a stack temporary, suitable for holding the
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/// specified value type. If minAlign is specified, the slot size will have
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/// at least that alignment.
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/// Create a stack temporary, suitable for holding the specified value type.
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/// If minAlign is specified, the slot size will have at least that alignment.
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SDValue CreateStackTemporary(EVT VT, unsigned minAlign = 1);
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/// Create a stack temporary suitable for holding
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/// either of the specified value types.
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/// Create a stack temporary suitable for holding either of the specified
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/// value types.
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SDValue CreateStackTemporary(EVT VT1, EVT VT2);
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SDValue FoldSymbolOffset(unsigned Opcode, EVT VT,
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@ -1285,27 +1284,27 @@ public:
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/// is set.
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bool isKnownToBeAPowerOfTwo(SDValue Val) const;
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/// Return the number of times the sign bit of the
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/// register is replicated into the other bits. We know that at least 1 bit
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/// is always equal to the sign bit (itself), but other cases can give us
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/// information. For example, immediately after an "SRA X, 2", we know that
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/// the top 3 bits are all equal to each other, so we return 3. Targets can
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/// implement the ComputeNumSignBitsForTarget method in the TargetLowering
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/// class to allow target nodes to be understood.
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/// Return the number of times the sign bit of the register is replicated into
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/// the other bits. We know that at least 1 bit is always equal to the sign
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/// bit (itself), but other cases can give us information. For example,
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/// immediately after an "SRA X, 2", we know that the top 3 bits are all equal
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/// to each other, so we return 3. Targets can implement the
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/// ComputeNumSignBitsForTarget method in the TargetLowering class to allow
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/// target nodes to be understood.
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unsigned ComputeNumSignBits(SDValue Op, unsigned Depth = 0) const;
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/// Return true if the specified operand is an
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/// ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an
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/// ISD::OR with a ConstantSDNode that is guaranteed to have the same
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/// semantics as an ADD. This handles the equivalence:
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/// Return true if the specified operand is an ISD::ADD with a ConstantSDNode
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/// on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that
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/// is guaranteed to have the same semantics as an ADD. This handles the
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/// equivalence:
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/// X|Cst == X+Cst iff X&Cst = 0.
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bool isBaseWithConstantOffset(SDValue Op) const;
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/// Test whether the given SDValue is known to never be NaN.
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bool isKnownNeverNaN(SDValue Op) const;
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/// Test whether the given SDValue is known to never be
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/// positive or negative Zero.
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/// Test whether the given SDValue is known to never be positive or negative
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/// zero.
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bool isKnownNeverZero(SDValue Op) const;
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/// Test whether two SDValues are known to compare equal. This
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@ -1364,6 +1363,7 @@ public:
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void ExtractVectorElements(SDValue Op, SmallVectorImpl<SDValue> &Args,
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unsigned Start = 0, unsigned Count = 0);
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/// Compute the default alignment value for the given type.
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unsigned getEVTAlignment(EVT MemoryVT) const;
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/// Test whether the given value is a constant int or similar node.
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@ -245,8 +245,6 @@ ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) {
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llvm_unreachable("Invalid LoadExtType");
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}
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/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
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/// when given the operation for (X op Y).
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ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
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// To perform this operation, we just need to swap the L and G bits of the
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// operation.
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@ -257,8 +255,6 @@ ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
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(OldG << 2)); // New L bit.
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}
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/// getSetCCInverse - Return the operation corresponding to !(X op Y), where
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/// 'op' is a valid SetCC operation.
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ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
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unsigned Operation = Op;
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if (isInteger)
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@ -273,9 +269,9 @@ ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
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}
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/// isSignedOp - For an integer comparison, return 1 if the comparison is a
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/// signed operation and 2 if the result is an unsigned comparison. Return zero
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/// if the operation does not depend on the sign of the input (setne and seteq).
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/// For an integer comparison, return 1 if the comparison is a signed operation
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/// and 2 if the result is an unsigned comparison. Return zero if the operation
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/// does not depend on the sign of the input (setne and seteq).
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static int isSignedOp(ISD::CondCode Opcode) {
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switch (Opcode) {
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default: llvm_unreachable("Illegal integer setcc operation!");
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@ -292,10 +288,6 @@ static int isSignedOp(ISD::CondCode Opcode) {
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}
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}
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/// getSetCCOrOperation - Return the result of a logical OR between different
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/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function
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/// returns SETCC_INVALID if it is not possible to represent the resultant
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/// comparison.
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ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
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bool isInteger) {
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if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
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@ -316,10 +308,6 @@ ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
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return ISD::CondCode(Op);
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}
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/// getSetCCAndOperation - Return the result of a logical AND between different
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/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
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/// function returns zero if it is not possible to represent the resultant
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/// comparison.
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ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
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bool isInteger) {
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if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
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@ -884,9 +872,6 @@ SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, ArrayRef<SDValue> Ops,
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return Node;
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}
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/// getEVTAlignment - Compute the default alignment value for the
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/// given type.
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///
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unsigned SelectionDAG::getEVTAlignment(EVT VT) const {
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Type *Ty = VT == MVT::iPTR ?
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PointerType::get(Type::getInt8Ty(*getContext()), 0) :
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@ -1480,9 +1465,8 @@ SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
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return SDValue(CondCodeNodes[Cond], 0);
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}
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// commuteShuffle - swaps the values of N1 and N2, and swaps all indices in
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// the shuffle mask M that point at N1 to point at N2, and indices that point
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// N2 to point at N1.
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/// Swaps the values of N1 and N2. Swaps all indices in the shuffle mask M that
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/// point at N1 to point at N2 and indices that point at N2 to point at N1.
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static void commuteShuffle(SDValue &N1, SDValue &N2, MutableArrayRef<int> M) {
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std::swap(N1, N2);
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ShuffleVectorSDNode::commuteMask(M);
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@ -1737,7 +1721,6 @@ SDValue SelectionDAG::getEHLabel(const SDLoc &dl, SDValue Root,
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return SDValue(N, 0);
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}
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SDValue SelectionDAG::getBlockAddress(const BlockAddress *BA, EVT VT,
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int64_t Offset,
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bool isTarget,
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@ -1777,7 +1760,6 @@ SDValue SelectionDAG::getSrcValue(const Value *V) {
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return SDValue(N, 0);
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}
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/// getMDNode - Return an MDNodeSDNode which holds an MDNode.
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SDValue SelectionDAG::getMDNode(const MDNode *MD) {
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FoldingSetNodeID ID;
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AddNodeIDNode(ID, ISD::MDNODE_SDNODE, getVTList(MVT::Other), None);
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@ -1800,7 +1782,6 @@ SDValue SelectionDAG::getBitcast(EVT VT, SDValue V) {
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return getNode(ISD::BITCAST, SDLoc(V), VT, V);
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}
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/// getAddrSpaceCast - Return an AddrSpaceCastSDNode.
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SDValue SelectionDAG::getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr,
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unsigned SrcAS, unsigned DestAS) {
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SDValue Ops[] = {Ptr};
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@ -1883,8 +1864,6 @@ SDValue SelectionDAG::expandVACopy(SDNode *Node) {
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MachinePointerInfo(VD), false, false, 0);
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}
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/// CreateStackTemporary - Create a stack temporary, suitable for holding the
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/// specified value type.
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SDValue SelectionDAG::CreateStackTemporary(EVT VT, unsigned minAlign) {
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MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
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unsigned ByteSize = VT.getStoreSize();
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@ -1896,8 +1875,6 @@ SDValue SelectionDAG::CreateStackTemporary(EVT VT, unsigned minAlign) {
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return getFrameIndex(FrameIdx, TLI->getPointerTy(getDataLayout()));
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}
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/// CreateStackTemporary - Create a stack temporary suitable for holding
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/// either of the specified value types.
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SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) {
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unsigned Bytes = std::max(VT1.getStoreSize(), VT2.getStoreSize());
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Type *Ty1 = VT1.getTypeForEVT(*getContext());
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@ -2547,11 +2524,6 @@ bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val) const {
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(KnownOne.countPopulation() == 1);
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}
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/// ComputeNumSignBits - Return the number of times the sign bit of the
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/// register is replicated into the other bits. We know that at least 1 bit
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/// is always equal to the sign bit (itself), but other cases can give us
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/// information. For example, immediately after an "SRA X, 2", we know that
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/// the top 3 bits are all equal to each other, so we return 3.
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unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const {
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EVT VT = Op.getValueType();
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assert(VT.isInteger() && "Invalid VT!");
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@ -2802,11 +2774,6 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
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return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros()));
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}
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/// isBaseWithConstantOffset - Return true if the specified operand is an
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/// ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an
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/// ISD::OR with a ConstantSDNode that is guaranteed to have the same
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/// semantics as an ADD. This handles the equivalence:
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/// X|Cst == X+Cst iff X&Cst = 0.
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bool SelectionDAG::isBaseWithConstantOffset(SDValue Op) const {
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if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
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!isa<ConstantSDNode>(Op.getOperand(1)))
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@ -2820,7 +2787,6 @@ bool SelectionDAG::isBaseWithConstantOffset(SDValue Op) const {
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return true;
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}
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bool SelectionDAG::isKnownNeverNaN(SDValue Op) const {
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// If we're told that NaNs won't happen, assume they won't.
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if (getTarget().Options.NoNaNsFPMath)
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@ -2914,8 +2880,7 @@ static SDValue FoldCONCAT_VECTORS(const SDLoc &DL, EVT VT,
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return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts);
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}
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/// getNode - Gets or creates the specified node.
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///
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/// Gets or creates the specified node.
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SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT) {
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FoldingSetNodeID ID;
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AddNodeIDNode(ID, Opcode, getVTList(VT), None);
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