From 6bf4f263ac1df62369582d4e49fe493e79ed80c4 Mon Sep 17 00:00:00 2001 From: Justin Hibbits Date: Mon, 23 Mar 2020 20:09:45 -0500 Subject: [PATCH] [PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32 Summary: The linker is free to relax this (relocation R_PPC_GOT_TPREL16) against R_PPC_TLS, if it sees fit (initial exec to local exec). If r0 is used, this can generate execution-invalid code (converts to 'addi %rX, %r0, FOO, which translates in PPC-lingo to li %rX, FOO). Forbid this instead. This fixes static binaries using locales on FreeBSD/powerpc (tested on FreeBSD/powerpcspe). Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D76662 --- lib/Target/PowerPC/PPCInstr64Bit.td | 2 +- lib/Target/PowerPC/PPCInstrInfo.td | 2 +- test/CodeGen/PowerPC/tls.ll | 16 ++++++++-------- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index c4142af11a9..542225ca0d1 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -1127,7 +1127,7 @@ def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16 (PPCaddisGotTprelHA i64:$reg, tglobaltlsaddr:$disp))]>, isPPC64; -def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), +def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), "#LDgotTprelL", [(set i64:$rD, (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 180826b0fa8..6c48512d8fb 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -3213,7 +3213,7 @@ def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", []>, NoEncode<"$rT">; -def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg), +def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), "#LDgotTprelL32", [(set i32:$rD, (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; diff --git a/test/CodeGen/PowerPC/tls.ll b/test/CodeGen/PowerPC/tls.ll index 18ca23b5e81..c5570e175f9 100644 --- a/test/CodeGen/PowerPC/tls.ll +++ b/test/CodeGen/PowerPC/tls.ll @@ -11,11 +11,11 @@ ;OPT1-LABEL: localexec: define i32 @localexec() nounwind { entry: -;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha -;OPT0-NEXT: addi [[REG2:[0-9]+]], [[REG1]], a@tprel@l +;OPT0: addis [[REG1:[1-9][0-9]*]], 13, a@tprel@ha +;OPT0-NEXT: addi [[REG2:[1-9][0-9]*]], [[REG1]], a@tprel@l ;OPT0-NEXT: li [[REG3:[0-9]+]], 42 ;OPT0: stw [[REG3]], 0([[REG2]]) -;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha +;OPT1: addis [[REG1:[1-9][0-9]*]], 13, a@tprel@ha ;OPT1-NEXT: li [[REG3:[0-9]+]], 42 ;OPT1: stw [[REG3]], a@tprel@l([[REG1]]) store i32 42, i32* @a, align 4 @@ -36,19 +36,19 @@ entry: } ; OPT1-LABEL: main2: -; OPT1: addis [[REG1:[0-9]+]], 2, a2@got@tprel@ha +; OPT1: addis [[REG1:[1-9][0-9]*]], 2, a2@got@tprel@ha ; OPT1: ld [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]]) ; OPT1: add {{[0-9]+}}, [[REG2]], a2@tls ;OPT0-PPC32-LABEL: main2: -;OPT0-PPC32: li [[REG1:[0-9]+]], _GLOBAL_OFFSET_TABLE_@l +;OPT0-PPC32: li [[REG1:[1-9][0-9]*]], _GLOBAL_OFFSET_TABLE_@l ;OPT0-PPC32: addis [[REG1]], [[REG1]], _GLOBAL_OFFSET_TABLE_@ha -;OPT0-PPC32: lwz [[REG2:[0-9]+]], a2@got@tprel([[REG1]]) +;OPT0-PPC32: lwz [[REG2:[1-9][0-9]*]], a2@got@tprel([[REG1]]) ;OPT0-PPC32: add 3, [[REG2]], a2@tls ;OPT0-PPC32-PIC-LABEL: main2: ;OPT0-PPC32-PIC: .long _GLOBAL_OFFSET_TABLE_-{{.*}} ;OPT0-PPC32-PIC-NOT: li {{[0-9]+}}, _GLOBAL_OFFSET_TABLE_@l -;OPT0-PPC32-PIC-NOT: addis {{[0-9]+}}, {{[0-9+]}}, _GLOBAL_OFFSET_TABLE_@ha +;OPT0-PPC32-PIC-NOT: addis {{[0-9]+}}, {{[1-9][0-9*]}}, _GLOBAL_OFFSET_TABLE_@ha ;OPT0-PPC32-PIC-NOT: bl __tls_get_addr(a2@tlsgd)@PLT -;OPT0-PPC32-PIC: lwz {{[0-9]+}}, a2@got@tprel({{[0-9]+}}) +;OPT0-PPC32-PIC: lwz {{[0-9]+}}, a2@got@tprel({{[1-9][0-9]*}})