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llvm-svn: 118199
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@ -255,7 +255,7 @@ unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI,
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// Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
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// shifted. The second is either Rs, the amount to shift by, or reg0 in which
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// case the imm contains the amount to shift by.
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//
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//
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// {3-0} = Rm.
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// {4} = 1 if reg shift, 0 if imm shift
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// {6-5} = type
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@ -349,7 +349,7 @@ unsigned ARMMCCodeEmitter::getAddrMode6AddressOpValue(const MCInst &MI,
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unsigned Op) const {
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const MCOperand &Reg = MI.getOperand(Op);
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const MCOperand &Imm = MI.getOperand(Op + 1);
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unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
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unsigned Align = 0;
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