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[AArch64]Select wide immediate offset into [Base+XReg] addressing mode
e.g Currently we'll generate following instructions if the immediate is too wide:
MOV X0, WideImmediate
ADD X1, BaseReg, X0
LDR X2, [X1, 0]
Using [Base+XReg] addressing mode can save one ADD as following:
MOV X0, WideImmediate
LDR X2, [BaseReg, X0]
Differential Revision: http://reviews.llvm.org/D5477
llvm-svn: 219665
This commit is contained in:
Hao Liu
parent
d5f6f42397
commit
6c7f917b92
@ -777,6 +777,21 @@ bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
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return false;
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}
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// Check if the given immediate is preferred by ADD. If an immediate can be
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// encoded in an ADD, or it can be encoded in an "ADD LSL #12" and can not be
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// encoded by one MOVZ, return true.
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static bool isPreferredADD(int64_t ImmOff) {
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// Constant in [0x0, 0xfff] can be encoded in ADD.
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if ((ImmOff & 0xfffffffffffff000LL) == 0x0LL)
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return true;
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// Check if it can be encoded in an "ADD LSL #12".
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if ((ImmOff & 0xffffffffff000fffLL) == 0x0LL)
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// As a single MOVZ is faster than a "ADD of LSL #12", ignore such constant.
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return (ImmOff & 0xffffffffff00ffffLL) != 0x0LL &&
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(ImmOff & 0xffffffffffff0fffLL) != 0x0LL;
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return false;
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}
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bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
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SDValue &Base, SDValue &Offset,
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SDValue &SignExtend,
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@ -786,11 +801,6 @@ bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
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SDValue LHS = N.getOperand(0);
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SDValue RHS = N.getOperand(1);
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// We don't want to match immediate adds here, because they are better lowered
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// to the register-immediate addressing modes.
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if (isa<ConstantSDNode>(LHS) || isa<ConstantSDNode>(RHS))
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return false;
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// Check if this particular node is reused in any non-memory related
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// operation. If yes, do not try to fold this node into the address
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// computation, since the computation will be kept.
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@ -800,6 +810,36 @@ bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
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return false;
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}
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// Watch out if RHS is a wide immediate, it can not be selected into
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// [BaseReg+Imm] addressing mode. Also it may not be able to be encoded into
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// ADD/SUB. Instead it will use [BaseReg + 0] address mode and generate
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// instructions like:
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// MOV X0, WideImmediate
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// ADD X1, BaseReg, X0
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// LDR X2, [X1, 0]
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// For such situation, using [BaseReg, XReg] addressing mode can save one
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// ADD/SUB:
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// MOV X0, WideImmediate
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// LDR X2, [BaseReg, X0]
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if (isa<ConstantSDNode>(RHS)) {
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int64_t ImmOff = (int64_t)dyn_cast<ConstantSDNode>(RHS)->getZExtValue();
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unsigned Scale = Log2_32(Size);
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// Skip the immediate can be seleced by load/store addressing mode.
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// Also skip the immediate can be encoded by a single ADD (SUB is also
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// checked by using -ImmOff).
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if ((ImmOff % Size == 0 && ImmOff >= 0 && ImmOff < (0x1000 << Scale)) ||
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isPreferredADD(ImmOff) || isPreferredADD(-ImmOff))
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return false;
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SDLoc DL(N.getNode());
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SDValue Ops[] = { RHS };
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SDNode *MOVI =
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CurDAG->getMachineNode(AArch64::MOVi64imm, DL, MVT::i64, Ops);
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SDValue MOVIV = SDValue(MOVI, 0);
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// This ADD of two X register will be selected into [Reg+Reg] mode.
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N = CurDAG->getNode(ISD::ADD, DL, MVT::i64, LHS, MOVIV);
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}
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// Remember if it is worth folding N when it produces extended register.
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bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
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@ -12,7 +12,7 @@ entry:
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for.body:
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; CHECK: for.body
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; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}]
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; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}, x{{[0-9]+}}]
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; CHECK: add x[[REG:[0-9]+]],
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; CHECK: x[[REG]], #1, lsl #12
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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@ -37,9 +37,8 @@ define void @t3() {
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; base + unsigned offset (> imm12 * size of type in bytes)
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; CHECK: @t4
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; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, #8, lsl #12
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; CHECK: ldr xzr, [
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; CHECK: [[ADDREG]]]
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; CHECK: orr w[[NUM:[0-9]+]], wzr, #0x8000
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; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
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; CHECK: ret
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define void @t4() {
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%incdec.ptr = getelementptr inbounds i64* @object, i64 4096
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@ -60,9 +59,8 @@ define void @t5(i64 %a) {
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; base + reg + imm
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; CHECK: @t6
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; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, x{{[0-9]+}}, lsl #3
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; CHECK-NEXT: add [[ADDREG]], [[ADDREG]], #8, lsl #12
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; CHECK: ldr xzr, [
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; CHECK: [[ADDREG]]]
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; CHECK-NEXT: orr w[[NUM:[0-9]+]], wzr, #0x8000
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; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
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; CHECK: ret
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define void @t6(i64 %a) {
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%tmp1 = getelementptr inbounds i64* @object, i64 %a
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@ -70,3 +68,114 @@ define void @t6(i64 %a) {
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%tmp = load volatile i64* %incdec.ptr, align 8
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ret void
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}
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; Test base + wide immediate
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define void @t7(i64 %a) {
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; CHECK-LABEL: t7:
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; CHECK: orr w[[NUM:[0-9]+]], wzr, #0xffff
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; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
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%1 = add i64 %a, 65535 ;0xffff
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64* %2, align 8
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ret void
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}
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define void @t8(i64 %a) {
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; CHECK-LABEL: t8:
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; CHECK: movn [[REG:x[0-9]+]], #0x1235
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; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
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%1 = sub i64 %a, 4662 ;-4662 is 0xffffffffffffedca
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64* %2, align 8
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ret void
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}
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define void @t9(i64 %a) {
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; CHECK-LABEL: t9:
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; CHECK: movn [[REG:x[0-9]+]], #0x1235, lsl #16
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; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
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%1 = add i64 -305463297, %a ;-305463297 is 0xffffffffedcaffff
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64* %2, align 8
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ret void
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}
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define void @t10(i64 %a) {
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; CHECK-LABEL: t10:
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; CHECK: movz [[REG:x[0-9]+]], #0x123, lsl #48
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; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
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%1 = add i64 %a, 81909218222800896 ;0x123000000000000
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64* %2, align 8
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ret void
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}
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define void @t11(i64 %a) {
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; CHECK-LABEL: t11:
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; CHECK: movz w[[NUM:[0-9]+]], #0x123, lsl #16
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; CHECK: movk w[[NUM:[0-9]+]], #0x4567
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; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
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%1 = add i64 %a, 19088743 ;0x1234567
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64* %2, align 8
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ret void
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}
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; Test some boundaries that should not use movz/movn/orr
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define void @t12(i64 %a) {
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; CHECK-LABEL: t12:
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; CHECK: add [[REG:x[0-9]+]], x0, #4095
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; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]]
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%1 = add i64 %a, 4095 ;0xfff
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64* %2, align 8
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ret void
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}
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define void @t13(i64 %a) {
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; CHECK-LABEL: t13:
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; CHECK: sub [[REG:x[0-9]+]], x0, #4095
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; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]]
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%1 = add i64 %a, -4095 ;-0xfff
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64* %2, align 8
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ret void
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}
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define void @t14(i64 %a) {
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; CHECK-LABEL: t14:
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; CHECK: add [[REG:x[0-9]+]], x0, #291, lsl #12
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; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]]
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%1 = add i64 %a, 1191936 ;0x123000
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64* %2, align 8
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ret void
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}
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define void @t15(i64 %a) {
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; CHECK-LABEL: t15:
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; CHECK: sub [[REG:x[0-9]+]], x0, #291, lsl #12
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; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]]
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%1 = add i64 %a, -1191936 ;0xFFFFFFFFFFEDD000
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64* %2, align 8
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ret void
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}
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define void @t16(i64 %a) {
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; CHECK-LABEL: t16:
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; CHECK: ldr xzr, [x0, #28672]
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%1 = add i64 %a, 28672 ;0x7000
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64* %2, align 8
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ret void
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}
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define void @t17(i64 %a) {
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; CHECK-LABEL: t17:
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; CHECK: ldur xzr, [x0, #-256]
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%1 = add i64 %a, -256 ;-0x100
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64* %2, align 8
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ret void
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}
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@ -172,9 +172,12 @@ define i32 @load_breg_immoff_5(i64 %a) {
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; Min un-supported scaled offset
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define i32 @load_breg_immoff_6(i64 %a) {
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; CHECK-LABEL: load_breg_immoff_6
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; CHECK: add [[REG:x[0-9]+]], x0, #4, lsl #12
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; CHECK-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
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; SDAG-LABEL: load_breg_immoff_6
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; SDAG: orr w[[NUM:[0-9]+]], wzr, #0x4000
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; SDAG-NEXT: ldr {{w[0-9]+}}, [x0, x[[NUM]]]
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; FAST-LABEL: load_breg_immoff_6
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; FAST: add [[REG:x[0-9]+]], x0, #4, lsl #12
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; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, 16384
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32* %2
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@ -235,9 +238,12 @@ define void @store_breg_immoff_5(i64 %a) {
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; Min un-supported scaled offset
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define void @store_breg_immoff_6(i64 %a) {
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; CHECK-LABEL: store_breg_immoff_6
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; CHECK: add [[REG:x[0-9]+]], x0, #4, lsl #12
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; CHECK-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
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; SDAG-LABEL: store_breg_immoff_6
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; SDAG: orr w[[NUM:[0-9]+]], wzr, #0x4000
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; SDAG-NEXT: str wzr, [x0, x[[NUM]]]
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; FAST-LABEL: store_breg_immoff_6
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; FAST: add [[REG:x[0-9]+]], x0, #4, lsl #12
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; FAST-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, 16384
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%2 = inttoptr i64 %1 to i32*
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store i32 0, i32* %2
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@ -298,8 +304,8 @@ define i64 @load_breg_offreg_immoff_1(i64 %a, i64 %b) {
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define i64 @load_breg_offreg_immoff_2(i64 %a, i64 %b) {
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; SDAG-LABEL: load_breg_offreg_immoff_2
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; SDAG: add [[REG1:x[0-9]+]], x0, x1
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; SDAG-NEXT: add [[REG2:x[0-9]+]], [[REG1]], #15, lsl #12
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; SDAG-NEXT: ldr x0, {{\[}}[[REG2]]{{\]}}
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; SDAG-NEXT: orr w[[NUM:[0-9]+]], wzr, #0xf000
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; SDAG-NEXT: ldr x0, {{\[}}[[REG1]], x[[NUM]]]
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; FAST-LABEL: load_breg_offreg_immoff_2
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; FAST: add [[REG:x[0-9]+]], x0, #15, lsl #12
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; FAST-NEXT: ldr x0, {{\[}}[[REG]], x1{{\]}}
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