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[PowerPC] Support constrained vector fp/int conversion
This patch makes these operations legal, and add necessary codegen patterns. There's still some issue similar to D77033 for conversion from v1i128 type. But normal type tests synced in vector-constrained-fp-intrinsic are passed successfully. Reviewed By: uweigand Differential Revision: https://reviews.llvm.org/D83654
This commit is contained in:
Qiu Chaofan
parent
6072801a3e
commit
6cd03c3d8a
@ -824,6 +824,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::SELECT, MVT::v4i32,
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Subtarget.useCRBits() ? Legal : Expand);
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setOperationAction(ISD::STORE , MVT::v4i32, Legal);
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setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
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setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
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setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
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setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
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setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
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setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
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@ -1002,6 +1006,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
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setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
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setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
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setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
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setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
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setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
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setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
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@ -1010,6 +1018,14 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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// Custom handling for partial vectors of integers converted to
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// floating point. We already have optimal handling for v2i32 through
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// the DAG combine, so those aren't necessary.
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setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i8, Custom);
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setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i8, Custom);
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setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom);
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setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom);
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setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i8, Custom);
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setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i8, Custom);
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setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom);
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setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
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@ -8346,17 +8362,19 @@ static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl) {
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SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
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const SDLoc &dl) const {
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bool IsStrict = Op->isStrictFPOpcode();
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unsigned Opc = Op.getOpcode();
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assert((Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP) &&
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SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
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assert((Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP ||
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Opc == ISD::STRICT_UINT_TO_FP || Opc == ISD::STRICT_SINT_TO_FP) &&
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"Unexpected conversion type");
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assert((Op.getValueType() == MVT::v2f64 || Op.getValueType() == MVT::v4f32) &&
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"Supports conversions to v2f64/v4f32 only.");
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bool SignedConv = Opc == ISD::SINT_TO_FP;
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bool SignedConv = Opc == ISD::SINT_TO_FP || Opc == ISD::STRICT_SINT_TO_FP;
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bool FourEltRes = Op.getValueType() == MVT::v4f32;
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SDValue Wide = widenVec(DAG, Op.getOperand(0), dl);
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SDValue Wide = widenVec(DAG, Src, dl);
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EVT WideVT = Wide.getValueType();
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unsigned WideNumElts = WideVT.getVectorNumElements();
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MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64;
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@ -8381,7 +8399,7 @@ SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
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SDValue Extend;
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if (SignedConv) {
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Arrange = DAG.getBitcast(IntermediateVT, Arrange);
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EVT ExtVT = Op.getOperand(0).getValueType();
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EVT ExtVT = Src.getValueType();
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if (Subtarget.hasP9Altivec())
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ExtVT = EVT::getVectorVT(*DAG.getContext(), WideVT.getVectorElementType(),
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IntermediateVT.getVectorNumElements());
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@ -8391,6 +8409,10 @@ SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
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} else
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Extend = DAG.getNode(ISD::BITCAST, dl, IntermediateVT, Arrange);
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if (IsStrict)
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return DAG.getNode(Opc, dl, {Op.getValueType(), MVT::Other},
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{Op.getOperand(0), Extend});
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return DAG.getNode(Opc, dl, Op.getValueType(), Extend);
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}
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@ -10648,6 +10670,28 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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}
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}
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void PPCTargetLowering::LowerOperationWrapper(SDNode *N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const {
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SDValue Res = LowerOperation(SDValue(N, 0), DAG);
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if (!Res.getNode())
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return;
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// Take the return value as-is if original node has only one result.
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if (N->getNumValues() == 1) {
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Results.push_back(Res);
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return;
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}
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// New node should have the same number of results.
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assert((N->getNumValues() == Res->getNumValues()) &&
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"Lowering returned the wrong number of results!");
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for (unsigned i = 0; i < N->getNumValues(); ++i)
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Results.push_back(Res.getValue(i));
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}
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void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
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SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const {
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@ -753,6 +753,12 @@ namespace llvm {
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///
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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/// LowerOperationWrapper - Place custom new result values for node in
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/// Results.
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void LowerOperationWrapper(SDNode *N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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/// ReplaceNodeResults - Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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///
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@ -821,7 +821,7 @@ let hasSideEffects = 0 in {
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def XVCVDPSXDS : XX2Form<60, 472,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpsxds $XT, $XB", IIC_VecFP,
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[(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
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[(set v2i64:$XT, (any_fp_to_sint v2f64:$XB))]>;
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def XVCVDPSXWS : XX2Form<60, 216,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpsxws $XT, $XB", IIC_VecFP,
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@ -829,7 +829,7 @@ let hasSideEffects = 0 in {
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def XVCVDPUXDS : XX2Form<60, 456,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpuxds $XT, $XB", IIC_VecFP,
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[(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
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[(set v2i64:$XT, (any_fp_to_uint v2f64:$XB))]>;
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def XVCVDPUXWS : XX2Form<60, 200,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpuxws $XT, $XB", IIC_VecFP,
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@ -845,18 +845,18 @@ let hasSideEffects = 0 in {
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def XVCVSPSXWS : XX2Form<60, 152,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspsxws $XT, $XB", IIC_VecFP,
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[(set v4i32:$XT, (fp_to_sint v4f32:$XB))]>;
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[(set v4i32:$XT, (any_fp_to_sint v4f32:$XB))]>;
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def XVCVSPUXDS : XX2Form<60, 392,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspuxds $XT, $XB", IIC_VecFP, []>;
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def XVCVSPUXWS : XX2Form<60, 136,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspuxws $XT, $XB", IIC_VecFP,
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[(set v4i32:$XT, (fp_to_uint v4f32:$XB))]>;
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[(set v4i32:$XT, (any_fp_to_uint v4f32:$XB))]>;
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def XVCVSXDDP : XX2Form<60, 504,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvsxddp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
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[(set v2f64:$XT, (any_sint_to_fp v2i64:$XB))]>;
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def XVCVSXDSP : XX2Form<60, 440,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvsxdsp $XT, $XB", IIC_VecFP,
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@ -868,11 +868,11 @@ let hasSideEffects = 0 in {
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def XVCVSXWSP : XX2Form<60, 184,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvsxwsp $XT, $XB", IIC_VecFP,
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[(set v4f32:$XT, (sint_to_fp v4i32:$XB))]>;
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[(set v4f32:$XT, (any_sint_to_fp v4i32:$XB))]>;
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def XVCVUXDDP : XX2Form<60, 488,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvuxddp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
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[(set v2f64:$XT, (any_uint_to_fp v2i64:$XB))]>;
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def XVCVUXDSP : XX2Form<60, 424,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvuxdsp $XT, $XB", IIC_VecFP,
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@ -884,7 +884,7 @@ let hasSideEffects = 0 in {
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def XVCVUXWSP : XX2Form<60, 168,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvuxwsp $XT, $XB", IIC_VecFP,
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[(set v4f32:$XT, (uint_to_fp v4i32:$XB))]>;
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[(set v4f32:$XT, (any_uint_to_fp v4i32:$XB))]>;
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// Rounding Instructions respecting current rounding mode
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def XSRDPIC : XX2Form<60, 107,
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