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[AArch64][GlobalISel] Mark G_INTRINSIC_ROUND as a pre-isel floating point opcode
Add G_INTRINSIC_ROUND to isPreISelGenericFloatingPointOpcode to ensure that its input and output are assigned the correct register bank. Add a regbankselect test to verify that we get what we expect here. llvm-svn: 359044
This commit is contained in:
Jessica Paquette
parent
d56d3c5b3f
commit
6cf54d8ec9
@ -407,6 +407,7 @@ static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
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case TargetOpcode::G_FEXP:
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case TargetOpcode::G_FRINT:
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case TargetOpcode::G_INTRINSIC_TRUNC:
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case TargetOpcode::G_INTRINSIC_ROUND:
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return true;
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}
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return false;
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196
test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir
Normal file
196
test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir
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@ -0,0 +1,196 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -mattr=+fullfp16 %s -o - | FileCheck %s
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# CHECK-NOT: gpr
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...
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---
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name: test_f16.round
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $h0
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; CHECK-LABEL: name: test_f16.round
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; CHECK: liveins: $h0
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; CHECK: [[COPY:%[0-9]+]]:fpr(s16) = COPY $h0
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; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(s16) = G_INTRINSIC_ROUND [[COPY]]
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; CHECK: $h0 = COPY [[INTRINSIC_ROUND]](s16)
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; CHECK: RET_ReallyLR implicit $h0
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%0:_(s16) = COPY $h0
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%1:_(s16) = G_INTRINSIC_ROUND %0
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: test_f32.round
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $s0
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; CHECK-LABEL: name: test_f32.round
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; CHECK: liveins: $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
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; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(s32) = G_INTRINSIC_ROUND [[COPY]]
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; CHECK: $s0 = COPY [[INTRINSIC_ROUND]](s32)
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; CHECK: RET_ReallyLR implicit $s0
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%0:_(s32) = COPY $s0
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%1:_(s32) = G_INTRINSIC_ROUND %0
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: test_f64.round
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_f64.round
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
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; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(s64) = G_INTRINSIC_ROUND [[COPY]]
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; CHECK: $d0 = COPY [[INTRINSIC_ROUND]](s64)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(s64) = COPY $d0
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%1:_(s64) = G_INTRINSIC_ROUND %0
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$d0 = COPY %1(s64)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v8f16.round
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v8f16.round
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s16>) = COPY $q0
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; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<8 x s16>) = G_INTRINSIC_ROUND [[COPY]]
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; CHECK: $q0 = COPY [[INTRINSIC_ROUND]](<8 x s16>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<8 x s16>) = COPY $q0
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%1:_(<8 x s16>) = G_INTRINSIC_ROUND %0
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v4f16.round
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v4f16.round
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s16>) = COPY $d0
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; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<4 x s16>) = G_INTRINSIC_ROUND [[COPY]]
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; CHECK: $d0 = COPY [[INTRINSIC_ROUND]](<4 x s16>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<4 x s16>) = COPY $d0
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%1:_(<4 x s16>) = G_INTRINSIC_ROUND %0
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v2f32.round
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v2f32.round
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0
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; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<2 x s32>) = G_INTRINSIC_ROUND [[COPY]]
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; CHECK: $d0 = COPY [[INTRINSIC_ROUND]](<2 x s32>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = G_INTRINSIC_ROUND %0
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v4f32.round
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v4f32.round
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
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; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<4 x s32>) = G_INTRINSIC_ROUND [[COPY]]
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; CHECK: $q0 = COPY [[INTRINSIC_ROUND]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = G_INTRINSIC_ROUND %0
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f64.round
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v2f64.round
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
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; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<2 x s64>) = G_INTRINSIC_ROUND [[COPY]]
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; CHECK: $q0 = COPY [[INTRINSIC_ROUND]](<2 x s64>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<2 x s64>) = COPY $q0
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%1:_(<2 x s64>) = G_INTRINSIC_ROUND %0
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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