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[AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*
See bug 35148: https://bugs.llvm.org//show_bug.cgi?id=35148 Reviewers: tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D39492 llvm-svn: 318526
This commit is contained in:
Dmitry Preobrazhensky
parent
9965df7585
commit
6d12a70c62
@ -1077,10 +1077,7 @@ public:
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OptionalImmIndexMap &OptionalIdx);
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void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3PImpl(MCInst &Inst, const OperandVector &Operands,
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bool IsPacked);
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void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3P_NotPacked(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
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@ -4320,11 +4317,13 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
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cvtVOP3(Inst, Operands, OptionalIdx);
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}
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void AMDGPUAsmParser::cvtVOP3PImpl(MCInst &Inst,
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const OperandVector &Operands,
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bool IsPacked) {
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void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst,
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const OperandVector &Operands) {
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OptionalImmIndexMap OptIdx;
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int Opc = Inst.getOpcode();
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const int Opc = Inst.getOpcode();
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const MCInstrDesc &Desc = MII.get(Opc);
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const bool IsPacked = (Desc.TSFlags & SIInstrFlags::IsPacked) != 0;
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cvtVOP3(Inst, Operands, OptIdx);
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@ -4340,7 +4339,6 @@ void AMDGPUAsmParser::cvtVOP3PImpl(MCInst &Inst,
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int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);
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if (OpSelHiIdx != -1) {
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// TODO: Should we change the printing to match?
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int DefaultVal = IsPacked ? -1 : 0;
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addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,
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DefaultVal);
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@ -4402,15 +4400,6 @@ void AMDGPUAsmParser::cvtVOP3PImpl(MCInst &Inst,
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}
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}
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void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
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cvtVOP3PImpl(Inst, Operands, true);
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}
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void AMDGPUAsmParser::cvtVOP3P_NotPacked(MCInst &Inst,
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const OperandVector &Operands) {
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cvtVOP3PImpl(Inst, Operands, false);
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}
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//===----------------------------------------------------------------------===//
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// dpp
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//===----------------------------------------------------------------------===//
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@ -806,8 +806,8 @@ void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
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}
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static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
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bool HasDstSel) {
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int DefaultValue = (Mod == SISrcMods::OP_SEL_1);
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bool IsPacked, bool HasDstSel) {
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int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
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for (int I = 0; I < NumOps; ++I) {
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if (!!(Ops[I] & Mod) != DefaultValue)
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@ -843,7 +843,10 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
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Mod == SISrcMods::OP_SEL_0 &&
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MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
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if (allOpsDefaultValue(Ops, NumOps, Mod, HasDstSel))
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const bool IsPacked =
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MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
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if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
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return;
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O << Name;
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@ -82,7 +82,10 @@ enum : uint64_t {
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// Clamps hi component of register.
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// ClampLo and ClampHi set for packed clamp.
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ClampHi = UINT64_C(1) << 48
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ClampHi = UINT64_C(1) << 48,
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// Is a packed VOP3P instruction.
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IsPacked = UINT64_C(1) << 49
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};
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// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
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@ -115,6 +115,9 @@ class InstSI <dag outs, dag ins, string asm = "",
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// of a packed output register.
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field bit ClampHi = 0;
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// This bit indicates that this is a packed VOP3P instruction
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field bit IsPacked = 0;
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// These need to be kept in sync with the enum in SIInstrFlags.
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let TSFlags{0} = SALU;
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let TSFlags{1} = VALU;
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@ -168,6 +171,8 @@ class InstSI <dag outs, dag ins, string asm = "",
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let TSFlags{47} = ClampLo;
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let TSFlags{48} = ClampHi;
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let TSFlags{49} = IsPacked;
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let SchedRW = [Write32Bit];
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field bits<1> DisableSIDecoder = 0;
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@ -80,6 +80,7 @@ class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
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let isCodeGenOnly = 1;
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let UseNamedOperandTable = 1;
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let VOP3_OPSEL = isVop3OpSel;
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let IsPacked = P.IsPacked;
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string Mnemonic = opName;
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string AsmOperands = !if(isVop3OpSel,
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@ -114,12 +115,11 @@ class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
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let AsmVariantName = AMDGPUAsmVariants.VOP3;
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let AsmMatchConverter =
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!if(!and(P.IsPacked, isVOP3P),
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!if(isVOP3P,
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"cvtVOP3P",
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!if(isVOP3P, "cvtVOP3P_NotPacked",
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!if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
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"cvtVOP3",
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"")));
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!if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
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"cvtVOP3",
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""));
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VOPProfile Pfl = P;
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}
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@ -83,7 +83,7 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext(half %src0, half %src
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}
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; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
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; GFX9: v_mad_mix_f32 v0, v0, v1, v2 clamp{{$}}
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; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
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; GFX9: v_cvt_f16_f32_e32 v0, v0
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define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %src0, half %src1, half %src2) #0 {
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%src0.ext = fpext half %src0 to float
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@ -99,7 +99,7 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %
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; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 clamp{{$}}
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; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
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; GFX9-NEXT: s_setpc_b64
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define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt(half %src0, half %src1, half %src2) #0 {
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%src0.ext = fpext half %src0 to float
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@ -116,9 +116,9 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt(half
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; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2{{$}}
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; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]{{$}}
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; GFX9-NEXT: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v3
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; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 clamp{{$}}
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; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_setpc_b64
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define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use(half %src0, half %src1, half %src2) #0 {
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@ -4,7 +4,7 @@
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; GCN-LABEL: mixlo_simple:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[0,0,0]{{$}}
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2{{$}}
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; GFX9-NEXT: s_setpc_b64
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; CIVI: v_mac_f32_e32
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@ -16,7 +16,7 @@ define half @mixlo_simple(float %src0, float %src1, float %src2) #0 {
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}
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; GCN-LABEL: {{^}}v_mad_mixlo_f16_f16lo_f16lo_f16lo:
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; GFX9: v_mad_mixlo_f16 v0, v0, v1, v2{{$}}
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; GFX9: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]{{$}}
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; CI: v_mac_f32
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; CIVI: v_cvt_f16_f32
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define half @v_mad_mixlo_f16_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
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@ -79,8 +79,8 @@ define half @v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt(half %src0, half %src
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; operation only clobbers relevant lane.
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; GCN-LABEL: {{^}}v_mad_mix_v2f32:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2{{$}}
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; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1]{{$}}
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; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]{{$}}
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; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]{{$}}
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; GFX9-NEXT: v_mov_b32_e32 v0, v3
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; GFX9-NEXT: s_setpc_b64
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define <2 x half> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
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@ -94,9 +94,9 @@ define <2 x half> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half
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; GCN-LABEL: {{^}}v_mad_mix_v3f32:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6
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; GFX9-NEXT: v_mad_mixlo_f16 v1, v1, v4, v7
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; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6 op_sel_hi:[1,1,1]
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; GFX9-NEXT: v_mad_mixlo_f16 v1, v1, v4, v7 op_sel_hi:[1,1,1]
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; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8 op_sel_hi:[1,1,1]
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; GFX9-NEXT: s_setpc_b64
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define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half> %src2) #0 {
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%src0.ext = fpext <3 x half> %src0 to <3 x float>
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@ -109,10 +109,10 @@ define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half
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; GCN-LABEL: {{^}}v_mad_mix_v4f32:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4
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; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1]
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; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5
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; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1]
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; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
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; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
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; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5 op_sel_hi:[1,1,1]
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; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
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; GFX9-NEXT: v_mov_b32_e32 v0, v6
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; GFX9-NEXT: v_mov_b32_e32 v1, v2
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; GFX9-NEXT: s_setpc_b64
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@ -127,8 +127,8 @@ define <4 x half> @v_mad_mix_v4f32(<4 x half> %src0, <4 x half> %src1, <4 x half
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; FIXME: Fold clamp
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; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_postcvt:
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; GFX9: v_mad_mixlo_f16 v3, v0, v1, v2 clamp{{$}}
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; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] clamp{{$}}
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; GFX9: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
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; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp{{$}}
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; GFX9-NEXT: v_mov_b32_e32 v0, v3
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; GFX9-NEXT: s_setpc_b64
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define <2 x half> @v_mad_mix_v2f32_clamp_postcvt(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
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@ -145,10 +145,10 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt(<2 x half> %src0, <2 x half> %s
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; FIXME: Should be packed into 2 registers per argument?
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; GCN-LABEL: {{^}}v_mad_mix_v3f32_clamp_postcvt:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8 clamp
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; GFX9-NEXT: v_mad_mixhi_f16 v2, v0, v0, v0 op_sel_hi:[0,0,0] clamp
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6 clamp
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; GFX9-NEXT: v_mad_mixhi_f16 v0, v1, v4, v7 clamp
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; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8 op_sel_hi:[1,1,1] clamp
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; GFX9-NEXT: v_mad_mixhi_f16 v2, v0, v0, v0 clamp
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6 op_sel_hi:[1,1,1] clamp
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; GFX9-NEXT: v_mad_mixhi_f16 v0, v1, v4, v7 op_sel_hi:[1,1,1] clamp
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; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0
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; GFX9-NEXT: s_setpc_b64
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define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %src1, <3 x half> %src2) #0 {
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@ -164,10 +164,10 @@ define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %s
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; GCN-LABEL: {{^}}v_mad_mix_v4f32_clamp_postcvt:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 clamp
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; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] clamp
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; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5 clamp
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; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] clamp
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; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
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; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
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; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5 op_sel_hi:[1,1,1] clamp
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; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
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; GFX9-DAG: v_mov_b32_e32 v0, v6
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; GFX9-DAG: v_mov_b32_e32 v1, v2
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; GFX9: s_setpc_b64
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@ -184,8 +184,8 @@ define <4 x half> @v_mad_mix_v4f32_clamp_postcvt(<4 x half> %src0, <4 x half> %s
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; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_postcvt_lo:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 clamp
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; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1]
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; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
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; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
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; GFX9-NEXT: v_mov_b32_e32 v0, v3
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; GFX9-NEXT: s_setpc_b64
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define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_lo(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
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@ -203,8 +203,8 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_lo(<2 x half> %src0, <2 x half>
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; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_postcvt_hi:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2
|
||||
; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] clamp
|
||||
; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
|
||||
; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, v3
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_hi(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
|
||||
@ -222,8 +222,8 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_hi(<2 x half> %src0, <2 x half>
|
||||
|
||||
; FIXME: Should be able to use mixlo/mixhi
|
||||
; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_precvt:
|
||||
; GFX9: v_mad_mix_f32 v3, v0, v1, v2 clamp
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] clamp
|
||||
; GFX9: v_mad_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
|
||||
; GFX9: v_cvt_f16_f32_e32 v1, v3
|
||||
; GFX9: v_cvt_f16_f32_e32 v0, v0
|
||||
; GFX9: v_and_b32_e32 v1, 0xffff, v1
|
||||
@ -241,9 +241,9 @@ define <2 x half> @v_mad_mix_v2f32_clamp_precvt(<2 x half> %src0, <2 x half> %sr
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_v3f32_clamp_precvt:
|
||||
; GFX9: v_mad_mix_f32 v0, v0, v3, v6 clamp
|
||||
; GFX9: v_mad_mix_f32 v1, v1, v4, v7 clamp
|
||||
; GFX9: v_mad_mix_f32 v2, v2, v5, v8 clamp
|
||||
; GFX9: v_mad_mix_f32 v0, v0, v3, v6 op_sel_hi:[1,1,1] clamp
|
||||
; GFX9: v_mad_mix_f32 v1, v1, v4, v7 op_sel_hi:[1,1,1] clamp
|
||||
; GFX9: v_mad_mix_f32 v2, v2, v5, v8 op_sel_hi:[1,1,1] clamp
|
||||
; GFX9: v_cvt_f16_f32
|
||||
; GFX9: v_cvt_f16_f32
|
||||
; GFX9: v_cvt_f16_f32
|
||||
@ -259,10 +259,10 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_v4f32_clamp_precvt:
|
||||
; GFX9: v_mad_mix_f32 v6, v0, v2, v4 op_sel:[1,1,1] clamp
|
||||
; GFX9: v_mad_mix_f32 v0, v0, v2, v4 clamp
|
||||
; GFX9: v_mad_mix_f32 v2, v1, v3, v5 op_sel:[1,1,1] clamp
|
||||
; GFX9: v_mad_mix_f32 v1, v1, v3, v5 clamp
|
||||
; GFX9: v_mad_mix_f32 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
|
||||
; GFX9: v_mad_mix_f32 v0, v0, v2, v4 op_sel_hi:[1,1,1] clamp
|
||||
; GFX9: v_mad_mix_f32 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
|
||||
; GFX9: v_mad_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
|
||||
; GFX9: v_cvt_f16_f32
|
||||
; GFX9: v_cvt_f16_f32
|
||||
; GFX9: v_cvt_f16_f32
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_f32_f16lo_f16lo_f16lo:
|
||||
; GFX9: v_mad_mix_f32 v0, v0, v1, v2 ; encoding: [0x00,0x40,0xa0,0xd3,0x00,0x03,0x0a,0x1c]
|
||||
; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] ; encoding: [0x00,0x40,0xa0,0xd3,0x00,0x03,0x0a,0x1c]
|
||||
; VI: v_mac_f32
|
||||
; CI: v_mad_f32
|
||||
define float @v_mad_mix_f32_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
|
||||
@ -15,7 +15,7 @@ define float @v_mad_mix_f32_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_f32_f16hi_f16hi_f16hi_int:
|
||||
; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] ; encoding
|
||||
; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] ; encoding
|
||||
; CIVI: v_mac_f32
|
||||
define float @v_mad_mix_f32_f16hi_f16hi_f16hi_int(i32 %src0, i32 %src1, i32 %src2) #0 {
|
||||
%src0.hi = lshr i32 %src0, 16
|
||||
@ -35,7 +35,7 @@ define float @v_mad_mix_f32_f16hi_f16hi_f16hi_int(i32 %src0, i32 %src1, i32 %src
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_f32_f16hi_f16hi_f16hi_elt:
|
||||
; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] ; encoding
|
||||
; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] ; encoding
|
||||
; VI: v_mac_f32
|
||||
; CI: v_mad_f32
|
||||
define float @v_mad_mix_f32_f16hi_f16hi_f16hi_elt(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
|
||||
@ -51,8 +51,8 @@ define float @v_mad_mix_f32_f16hi_f16hi_f16hi_elt(<2 x half> %src0, <2 x half> %
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_v2f32:
|
||||
; GFX9: v_mov_b32_e32 v3, v1
|
||||
; GFX9-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[1,1,1]
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, v0, v3, v2
|
||||
; GFX9-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, v0, v3, v2 op_sel_hi:[1,1,1]
|
||||
|
||||
; CIVI: v_mac_f32
|
||||
define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
|
||||
@ -66,8 +66,8 @@ define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x hal
|
||||
; GCN-LABEL: {{^}}v_mad_mix_v2f32_shuffle:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, v1
|
||||
; GFX9-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[0,1,1]
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, v0, v3, v2 op_sel:[1,0,1]
|
||||
; GFX9-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, v0, v3, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1]
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; CIVI: v_mac_f32
|
||||
@ -84,7 +84,7 @@ define <2 x float> @v_mad_mix_v2f32_shuffle(<2 x half> %src0, <2 x half> %src1,
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_f32_negf16lo_f16lo_f16lo:
|
||||
; GFX9: s_waitcnt
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 ; encoding
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1] ; encoding
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; CIVI: v_mad_f32
|
||||
@ -98,7 +98,7 @@ define float @v_mad_mix_f32_negf16lo_f16lo_f16lo(half %src0, half %src1, half %s
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_f32_absf16lo_f16lo_f16lo:
|
||||
; GFX9: v_mad_mix_f32 v0, |v0|, v1, v2
|
||||
; GFX9: v_mad_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
|
||||
|
||||
; CIVI: v_mad_f32
|
||||
define float @v_mad_mix_f32_absf16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
|
||||
@ -112,7 +112,7 @@ define float @v_mad_mix_f32_absf16lo_f16lo_f16lo(half %src0, half %src1, half %s
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_f32_negabsf16lo_f16lo_f16lo:
|
||||
; GFX9: s_waitcnt
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, -|v0|, v1, v2
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; CIVI: v_mad_f32
|
||||
@ -282,7 +282,7 @@ define <2 x float> @v_mad_mix_v2f32_f32imminv2pi(<2 x half> %src0, <2 x half> %s
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_clamp_f32_f16hi_f16hi_f16hi_elt:
|
||||
; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] clamp ; encoding
|
||||
; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp ; encoding
|
||||
; VI: v_mac_f32_e64 v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}} clamp{{$}}
|
||||
; CI: v_mad_f32 v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}} clamp{{$}}
|
||||
define float @v_mad_mix_clamp_f32_f16hi_f16hi_f16hi_elt(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
|
||||
@ -375,7 +375,7 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, half
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 ; encoding
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] ; encoding
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd(half %src0, half %src1, half %src2) #0 {
|
||||
%src0.ext = fpext half %src0 to float
|
||||
@ -400,7 +400,7 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32_flush_fmulfadd(half %src0, half %src
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
|
||||
; GFX9: s_waitcnt
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 ; encoding
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1] ; encoding
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; CIVI: v_mad_f32
|
||||
@ -433,7 +433,7 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo(i32 %src0.arg, half %
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
|
||||
; GFX9: s_waitcnt
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0]
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define float @v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
|
||||
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
|
||||
@ -448,7 +448,7 @@ define float @v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo(i32 %src0.arg, half %src1
|
||||
|
||||
; GCN-LABEL: {{^}}v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
|
||||
; GFX9: s_waitcnt
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0]
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define float @v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
|
||||
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
|
||||
@ -465,7 +465,7 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half
|
||||
; GCN-LABEL: {{^}}v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
|
||||
; GFX9: s_waitcnt
|
||||
; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,0,0]
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define float @v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
|
||||
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
|
||||
@ -482,7 +482,7 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo(i32 %src0.arg, half
|
||||
; GCN-LABEL: {{^}}v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
|
||||
; GFX9: s_waitcnt
|
||||
; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0]
|
||||
; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
|
||||
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
|
||||
|
||||
@ -169,78 +169,78 @@ v_pk_max_f16 v0, v1, v2
|
||||
// GFX9: v_pk_max_f16 v0, v1, v2 ; encoding: [0x00,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
|
||||
|
||||
v_mad_mix_f32 v0, v1, v2, v3
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mixlo_f16 v0, v1, v2, v3
|
||||
// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mixhi_f16 v0, v1, v2, v3
|
||||
// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
//
|
||||
// Regular source modifiers on non-packed instructions
|
||||
//
|
||||
|
||||
v_mad_mix_f32 v0, abs(v1), v2, v3
|
||||
// GFX9: v_mad_mix_f32 v0, |v1|, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mix_f32 v0, |v1|, v2, v3 ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mix_f32 v0, v1, abs(v2), v3
|
||||
// GFX9: v_mad_mix_f32 v0, v1, |v2|, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, |v2|, v3 ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mix_f32 v0, v1, v2, abs(v3)
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, |v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, |v3| ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mix_f32 v0, -v1, v2, v3
|
||||
// GFX9: v_mad_mix_f32 v0, -v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]
|
||||
// GFX9: v_mad_mix_f32 v0, -v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]
|
||||
|
||||
v_mad_mix_f32 v0, v1, -v2, v3
|
||||
// GFX9: v_mad_mix_f32 v0, v1, -v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, -v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]
|
||||
|
||||
v_mad_mix_f32 v0, v1, v2, -v3
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, -v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, -v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]
|
||||
|
||||
v_mad_mix_f32 v0, -abs(v1), v2, v3
|
||||
// GFX9: v_mad_mix_f32 v0, -|v1|, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x24]
|
||||
// GFX9: v_mad_mix_f32 v0, -|v1|, v2, v3 ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x24]
|
||||
|
||||
v_mad_mix_f32 v0, v1, -abs(v2), v3
|
||||
// GFX9: v_mad_mix_f32 v0, v1, -|v2|, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x44]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, -|v2|, v3 ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x44]
|
||||
|
||||
v_mad_mix_f32 v0, v1, v2, -abs(v3)
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, -|v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x84]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, -|v3| ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x84]
|
||||
|
||||
v_mad_mixlo_f16 v0, abs(v1), -v2, abs(v3)
|
||||
// GFX9: v_mad_mixlo_f16 v0, |v1|, -v2, |v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x05,0xa1,0xd3,0x01,0x05,0x0e,0x44]
|
||||
// GFX9: v_mad_mixlo_f16 v0, |v1|, -v2, |v3| ; encoding: [0x00,0x05,0xa1,0xd3,0x01,0x05,0x0e,0x44]
|
||||
|
||||
v_mad_mixhi_f16 v0, -v1, abs(v2), -abs(v3)
|
||||
// GFX9: v_mad_mixhi_f16 v0, -v1, |v2|, -|v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x06,0xa2,0xd3,0x01,0x05,0x0e,0xa4]
|
||||
// GFX9: v_mad_mixhi_f16 v0, -v1, |v2|, -|v3| ; encoding: [0x00,0x06,0xa2,0xd3,0x01,0x05,0x0e,0xa4]
|
||||
|
||||
v_mad_mixlo_f16 v0, v1, v2, v3 clamp
|
||||
// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] clamp ; encoding: [0x00,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mixhi_f16 v0, v1, v2, v3 clamp
|
||||
// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] clamp ; encoding: [0x00,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
//
|
||||
// op_sel with non-packed instructions
|
||||
//
|
||||
|
||||
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,0]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x00,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x00,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1] op_sel_hi:[0,0,0] ; encoding: [0x00,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x00,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1] op_sel_hi:[0,0,0] ; encoding: [0x00,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x00,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,0,0]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c]
|
||||
@ -252,7 +252,7 @@ v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,1]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,1] ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,1,1]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
|
||||
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,1,1] ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
|
||||
|
||||
v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp
|
||||
// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp ; encoding: [0x00,0xc0,0xa1,0xd3,0x01,0x05,0x0e,0x0c]
|
||||
|
||||
@ -188,3 +188,444 @@
|
||||
|
||||
# GFX9: v_mad_u16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v255, v1, v2, v3 ; encoding: [0xff,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0xff,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v255, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0xff,0x05,0x0e,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0xff,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, s1, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, s101, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x65,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x65,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, flat_scratch_lo, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x66,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x66,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, flat_scratch_hi, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x67,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x67,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x6a,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x6a,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, vcc_hi, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x6b,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x6b,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, m0, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x7c,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x7c,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, exec_lo, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x7e,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x7e,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, exec_hi, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x7f,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x7f,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v255, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0f,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0xff,0x0f,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, s2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0c,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, s101, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xcb,0x0c,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0xcb,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, flat_scratch_lo, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xcd,0x0c,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0xcd,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, flat_scratch_hi, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xcf,0x0c,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0xcf,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, vcc_lo, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xd5,0x0c,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0xd5,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, vcc_hi, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xd7,0x0c,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0xd7,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, m0, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xf9,0x0c,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0xf9,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, exec_lo, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xfd,0x0c,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0xfd,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, exec_hi, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0c,0x04]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0xff,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, v255 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x07]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x07
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x00]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x00
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, s101 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x96,0x01]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0x96,0x01
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, flat_scratch_lo ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x9a,0x01]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0x9a,0x01
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, flat_scratch_hi ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x9e,0x01]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0x9e,0x01
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, vcc_lo ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xaa,0x01]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0xaa,0x01
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, vcc_hi ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xae,0x01]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0xae,0x01
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, m0 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xf2,0x01]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0xf2,0x01
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, exec_lo ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfa,0x01]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0xfa,0x01
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, exec_hi ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x01]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x01
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x05,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x05,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x05,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x05,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,1] ; encoding: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,1,1] ; encoding: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
|
||||
0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, -v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0xe4]
|
||||
0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0xe4
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, |v1|, v2, v3 ; encoding: [0x05,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x07,0xa0,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mix_f32 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xa0,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0xa0,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v255, v1, v2, v3 ; encoding: [0xff,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0xff,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v255, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0xff,0x05,0x0e,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0xff,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, s1, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, s101, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x65,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x65,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, flat_scratch_lo, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x66,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x66,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, flat_scratch_hi, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x67,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x67,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x6a,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x6a,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, vcc_hi, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x6b,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x6b,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, m0, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x7c,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x7c,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, exec_lo, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x7e,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x7e,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, exec_hi, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x7f,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x7f,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v255, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xff,0x0f,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0xff,0x0f,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, s2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0c,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, s101, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xcb,0x0c,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0xcb,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, flat_scratch_lo, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xcd,0x0c,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0xcd,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, flat_scratch_hi, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xcf,0x0c,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0xcf,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, vcc_lo, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xd5,0x0c,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0xd5,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, vcc_hi, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xd7,0x0c,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0xd7,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, m0, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xf9,0x0c,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0xf9,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, exec_lo, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xfd,0x0c,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0xfd,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, exec_hi, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xff,0x0c,0x04]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0xff,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, v255 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x07]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x07
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, s3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x00]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x00
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, s101 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x96,0x01]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0x96,0x01
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, flat_scratch_lo ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x9a,0x01]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0x9a,0x01
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, flat_scratch_hi ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x9e,0x01]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0x9e,0x01
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, vcc_lo ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xaa,0x01]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0xaa,0x01
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, vcc_hi ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xae,0x01]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0xae,0x01
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, m0 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xf2,0x01]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0xf2,0x01
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, exec_lo ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfa,0x01]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0xfa,0x01
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, exec_hi ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x01]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x01
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x05,0x08,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x08,0xa2,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x05,0x10,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x10,0xa2,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x05,0x20,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x20,0xa2,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x05,0x38,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x38,0xa2,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x0c]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x0c
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x14]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x14
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1] ; encoding: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1] ; encoding: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
|
||||
0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x24]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x24
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x44]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x44
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, -v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x84]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x84
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0xe4]
|
||||
0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0xe4
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, |v1|, v2, v3 ; encoding: [0x05,0x01,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x01,0xa2,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x02,0xa2,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x04,0xa2,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x07,0xa2,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v255, v1, v2, v3 ; encoding: [0xff,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0xff,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v255, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0xff,0x05,0x0e,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0xff,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, s1, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, s101, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x65,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x65,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, flat_scratch_lo, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x66,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x66,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, flat_scratch_hi, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x67,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x67,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x6a,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x6a,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, vcc_hi, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x6b,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x6b,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, m0, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x7c,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x7c,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, exec_lo, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x7e,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x7e,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, exec_hi, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x7f,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x7f,0x04,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v255, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xff,0x0f,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0xff,0x0f,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, s2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0c,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, s101, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xcb,0x0c,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0xcb,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, flat_scratch_lo, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xcd,0x0c,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0xcd,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, flat_scratch_hi, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xcf,0x0c,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0xcf,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, vcc_lo, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xd5,0x0c,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0xd5,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, vcc_hi, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xd7,0x0c,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0xd7,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, m0, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xf9,0x0c,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0xf9,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, exec_lo, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xfd,0x0c,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0xfd,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, exec_hi, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xff,0x0c,0x04]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0xff,0x0c,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v255 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x07]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x07
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, s3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x00]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x00
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, s101 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x96,0x01]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0x96,0x01
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, flat_scratch_lo ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x9a,0x01]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0x9a,0x01
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, flat_scratch_hi ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x9e,0x01]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0x9e,0x01
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, vcc_lo ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xaa,0x01]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0xaa,0x01
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, vcc_hi ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xae,0x01]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0xae,0x01
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, m0 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xf2,0x01]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0xf2,0x01
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, exec_lo ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfa,0x01]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0xfa,0x01
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, exec_hi ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x01]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x01
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x05,0x08,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x08,0xa1,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x05,0x10,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x10,0xa1,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x05,0x20,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x20,0xa1,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x05,0x38,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x38,0xa1,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x0c]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x0c
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x14]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x14
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1] ; encoding: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1] ; encoding: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
|
||||
0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x24]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x24
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x44]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x44
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, -v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x84]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x84
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0xe4]
|
||||
0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0xe4
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, |v1|, v2, v3 ; encoding: [0x05,0x01,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x01,0xa1,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x02,0xa1,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x04,0xa1,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x07,0xa1,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user