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[AArch64] Favor extended reg patterns for sub
Summary: Favor the extended reg patterns over the shifted reg patterns that match only the operand shift and not the full sign/zero extend and shift. Reviewers: jmolloy, t.p.northover Subscribers: mcrosier, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11569 llvm-svn: 243753
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Geoff Berry
parent
cdfefab4f7
commit
6d2bb54f01
@ -613,10 +613,12 @@ def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
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(SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
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def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
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(SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
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let AddedComplexity = 1 in {
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def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
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(SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
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def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
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(SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
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}
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// Because of the immediate format for add/sub-imm instructions, the
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// expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
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@ -80,6 +80,64 @@ end:
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ret void
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}
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define void @sub_i8rhs() minsize {
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; CHECK-LABEL: sub_i8rhs:
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%val8_tmp = load i8, i8* @var8
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%lhs32 = load i32, i32* @var32
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%lhs64 = load i64, i64* @var64
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; Need this to prevent extension upon load and give a vanilla i8 operand.
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%val8 = add i8 %val8_tmp, 123
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; Zero-extending to 32-bits
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%rhs32_zext = zext i8 %val8 to i32
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%res32_zext = sub i32 %lhs32, %rhs32_zext
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store volatile i32 %res32_zext, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
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%rhs32_zext_shift = shl i32 %rhs32_zext, 3
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%res32_zext_shift = sub i32 %lhs32, %rhs32_zext_shift
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store volatile i32 %res32_zext_shift, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
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; Zero-extending to 64-bits
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%rhs64_zext = zext i8 %val8 to i64
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%res64_zext = sub i64 %lhs64, %rhs64_zext
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store volatile i64 %res64_zext, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
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%rhs64_zext_shift = shl i64 %rhs64_zext, 1
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%res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
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store volatile i64 %res64_zext_shift, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
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; Sign-extending to 32-bits
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%rhs32_sext = sext i8 %val8 to i32
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%res32_sext = sub i32 %lhs32, %rhs32_sext
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store volatile i32 %res32_sext, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb
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%rhs32_sext_shift = shl i32 %rhs32_sext, 1
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%res32_sext_shift = sub i32 %lhs32, %rhs32_sext_shift
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store volatile i32 %res32_sext_shift, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb #1
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; Sign-extending to 64-bits
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%rhs64_sext = sext i8 %val8 to i64
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%res64_sext = sub i64 %lhs64, %rhs64_sext
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store volatile i64 %res64_sext, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb
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%rhs64_sext_shift = shl i64 %rhs64_sext, 4
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%res64_sext_shift = sub i64 %lhs64, %rhs64_sext_shift
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store volatile i64 %res64_sext_shift, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb #4
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ret void
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}
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define void @addsub_i16rhs() minsize {
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; CHECK-LABEL: addsub_i16rhs:
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%val16_tmp = load i16, i16* @var16
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@ -155,6 +213,64 @@ end:
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ret void
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}
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define void @sub_i16rhs() minsize {
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; CHECK-LABEL: sub_i16rhs:
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%val16_tmp = load i16, i16* @var16
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%lhs32 = load i32, i32* @var32
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%lhs64 = load i64, i64* @var64
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; Need this to prevent extension upon load and give a vanilla i16 operand.
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%val16 = add i16 %val16_tmp, 123
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; Zero-extending to 32-bits
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%rhs32_zext = zext i16 %val16 to i32
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%res32_zext = sub i32 %lhs32, %rhs32_zext
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store volatile i32 %res32_zext, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
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%rhs32_zext_shift = shl i32 %rhs32_zext, 3
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%res32_zext_shift = sub i32 %lhs32, %rhs32_zext_shift
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store volatile i32 %res32_zext_shift, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
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; Zero-extending to 64-bits
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%rhs64_zext = zext i16 %val16 to i64
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%res64_zext = sub i64 %lhs64, %rhs64_zext
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store volatile i64 %res64_zext, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
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%rhs64_zext_shift = shl i64 %rhs64_zext, 1
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%res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
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store volatile i64 %res64_zext_shift, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
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; Sign-extending to 32-bits
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%rhs32_sext = sext i16 %val16 to i32
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%res32_sext = sub i32 %lhs32, %rhs32_sext
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store volatile i32 %res32_sext, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
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%rhs32_sext_shift = shl i32 %rhs32_sext, 1
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%res32_sext_shift = sub i32 %lhs32, %rhs32_sext_shift
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store volatile i32 %res32_sext_shift, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth #1
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; Sign-extending to 64-bits
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%rhs64_sext = sext i16 %val16 to i64
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%res64_sext = sub i64 %lhs64, %rhs64_sext
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store volatile i64 %res64_sext, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth
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%rhs64_sext_shift = shl i64 %rhs64_sext, 4
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%res64_sext_shift = sub i64 %lhs64, %rhs64_sext_shift
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store volatile i64 %res64_sext_shift, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth #4
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ret void
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}
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; N.b. we could probably check more here ("add w2, w3, w1, uxtw" for
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; example), but the remaining instructions are probably not idiomatic
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; in the face of "add/sub (shifted register)" so I don't intend to.
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@ -187,3 +303,33 @@ define void @addsub_i32rhs() minsize {
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ret void
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}
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define void @sub_i32rhs() minsize {
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; CHECK-LABEL: sub_i32rhs:
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%val32_tmp = load i32, i32* @var32
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%lhs64 = load i64, i64* @var64
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%val32 = add i32 %val32_tmp, 123
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%rhs64_zext = zext i32 %val32 to i64
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%res64_zext = sub i64 %lhs64, %rhs64_zext
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store volatile i64 %res64_zext, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
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%rhs64_zext_shift = shl i64 %rhs64_zext, 2
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%res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
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store volatile i64 %res64_zext_shift, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
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%rhs64_sext = sext i32 %val32 to i64
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%res64_sext = sub i64 %lhs64, %rhs64_sext
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store volatile i64 %res64_sext, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
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%rhs64_sext_shift = shl i64 %rhs64_sext, 2
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%res64_sext_shift = sub i64 %lhs64, %rhs64_sext_shift
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store volatile i64 %res64_sext_shift, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2
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ret void
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}
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