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[X86] Regenerate x64 mmx/f64 return value tests
llvm-svn: 280634
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@ -1,40 +1,49 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -mcpu=core2 -mattr=+mmx,+sse2 | FileCheck %s
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; rdar://6602459
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@g_v1di = external global <1 x i64>
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define void @t1() nounwind {
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entry:
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%call = call <1 x i64> @return_v1di() ; <<1 x i64>> [#uses=0]
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store <1 x i64> %call, <1 x i64>* @g_v1di
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ret void
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; CHECK-LABEL: t1:
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; CHECK: callq
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; CHECK-NEXT: movq _g_v1di
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; CHECK-NEXT: movq %rax,
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: callq _return_v1di
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; CHECK-NEXT: movq _g_v1di@{{.*}}(%rip), %rcx
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; CHECK-NEXT: movq %rax, (%rcx)
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; CHECK-NEXT: popq %rax
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; CHECK-NEXT: retq
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entry:
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%call = call <1 x i64> @return_v1di() ; <<1 x i64>> [#uses=0]
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store <1 x i64> %call, <1 x i64>* @g_v1di
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ret void
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}
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declare <1 x i64> @return_v1di()
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define <1 x i64> @t2() nounwind {
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ret <1 x i64> <i64 1>
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; CHECK-LABEL: t2:
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; CHECK: movl $1
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; CHECK-NEXT: ret
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retq
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ret <1 x i64> <i64 1>
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}
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define <2 x i32> @t3() nounwind {
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ret <2 x i32> <i32 1, i32 0>
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; CHECK-LABEL: t3:
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; CHECK: movl $1
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; CHECK: movd {{.*}}, %xmm0
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: movd %rax, %xmm0
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; CHECK-NEXT: retq
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ret <2 x i32> <i32 1, i32 0>
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}
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define double @t4() nounwind {
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ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
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; CHECK-LABEL: t4:
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; CHECK: movl $1
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; CHECK-NOT: pshufd
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; CHECK: movd {{.*}}, %xmm0
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: movd %eax, %xmm0
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; CHECK-NEXT: retq
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ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
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}
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