From 6d8eb7f2807e03e3fa9a3a3cbf264b04adae3848 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 11 Apr 2019 15:29:15 +0000 Subject: [PATCH] [X86] SimplifyDemandedVectorElts - add X86ISD::VPERMV3 mask support Completes SimplifyDemandedVectorElts's basic variable shuffle mask support which should help D60512 + D60562 llvm-svn: 358186 --- lib/Target/X86/X86ISelLowering.cpp | 2 +- test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll | 6 ++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 60085493913..2258e0ce24e 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -33234,8 +33234,8 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode( break; } case X86ISD::PSHUFB: + case X86ISD::VPERMV3: case X86ISD::VPERMILPV: { - // TODO - simplify other variable shuffle masks. SDValue Mask = Op.getOperand(1); APInt MaskUndef, MaskZero; if (SimplifyDemandedVectorElts(Mask, DemandedElts, MaskUndef, MaskZero, TLO, diff --git a/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll b/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll index b180a517032..d796108aa5f 100644 --- a/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll +++ b/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll @@ -933,10 +933,8 @@ define <8 x double> @combine_vpermi2var_8f64_as_permpd(<8 x double> %x0, <8 x do ; ; X64-LABEL: combine_vpermi2var_8f64_as_permpd: ; X64: # %bb.0: -; X64-NEXT: vmovdqa {{.*#+}} xmm2 = -; X64-NEXT: vpinsrq $0, %rdi, %xmm2, %xmm2 -; X64-NEXT: vmovdqa64 {{.*#+}} zmm3 = -; X64-NEXT: vinserti32x4 $0, %xmm2, %zmm3, %zmm2 +; X64-NEXT: vmovapd {{.*#+}} zmm2 = +; X64-NEXT: vinsertf32x4 $0, {{.*}}(%rip), %zmm2, %zmm2 ; X64-NEXT: vpermi2pd %zmm1, %zmm0, %zmm2 ; X64-NEXT: vpermpd {{.*#+}} zmm0 = zmm2[2,3,1,1,6,7,5,5] ; X64-NEXT: retq