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[AArch64][GlobalISel] Implement selection for G_UNMERGE of vectors to vectors.
This re-uses the previous support for extract vector elt to extract the subvectors. Differential Revision: https://reviews.llvm.org/D59390 llvm-svn: 356213
This commit is contained in:
Amara Emerson
parent
90869d8494
commit
6da5735cc0
@ -93,6 +93,8 @@ private:
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bool selectShuffleVector(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool selectExtractElt(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool selectConcatVectors(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool selectSplitVectorUnmerge(MachineInstr &I,
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MachineRegisterInfo &MRI) const;
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unsigned emitConstantPoolEntry(Constant *CPVal, MachineFunction &MF) const;
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MachineInstr *emitLoadFromConstantPool(Constant *CPVal,
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@ -102,6 +104,10 @@ private:
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MachineInstr *emitVectorConcat(Optional<unsigned> Dst, unsigned Op1,
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unsigned Op2,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitExtractVectorElt(Optional<unsigned> DstReg,
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const RegisterBank &DstRB, LLT ScalarTy,
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unsigned VecReg, unsigned LaneIdx,
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MachineIRBuilder &MIRBuilder) const;
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ComplexRendererFns selectArithImmed(MachineOperand &Root) const;
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@ -1870,6 +1876,68 @@ static bool getConstantValueForReg(unsigned Reg, MachineRegisterInfo &MRI,
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return true;
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}
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MachineInstr *AArch64InstructionSelector::emitExtractVectorElt(
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Optional<unsigned> DstReg, const RegisterBank &DstRB, LLT ScalarTy,
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unsigned VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const {
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MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
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unsigned CopyOpc = 0;
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unsigned ExtractSubReg = 0;
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if (!getLaneCopyOpcode(CopyOpc, ExtractSubReg, ScalarTy.getSizeInBits())) {
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LLVM_DEBUG(
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dbgs() << "Couldn't determine lane copy opcode for instruction.\n");
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return nullptr;
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}
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const TargetRegisterClass *DstRC =
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getRegClassForTypeOnBank(ScalarTy, DstRB, RBI, true);
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if (!DstRC) {
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LLVM_DEBUG(dbgs() << "Could not determine destination register class.\n");
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return nullptr;
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}
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const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI);
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const LLT &VecTy = MRI.getType(VecReg);
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const TargetRegisterClass *VecRC =
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getRegClassForTypeOnBank(VecTy, VecRB, RBI, true);
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if (!VecRC) {
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LLVM_DEBUG(dbgs() << "Could not determine source register class.\n");
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return nullptr;
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}
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// The register that we're going to copy into.
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unsigned InsertReg = VecReg;
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if (!DstReg)
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DstReg = MRI.createVirtualRegister(DstRC);
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// If the lane index is 0, we just use a subregister COPY.
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if (LaneIdx == 0) {
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auto CopyMI =
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BuildMI(MIRBuilder.getMBB(), MIRBuilder.getInsertPt(),
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MIRBuilder.getDL(), TII.get(TargetOpcode::COPY), *DstReg)
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.addUse(VecReg, 0, ExtractSubReg);
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RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);
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return &*CopyMI;
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}
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// Lane copies require 128-bit wide registers. If we're dealing with an
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// unpacked vector, then we need to move up to that width. Insert an implicit
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// def and a subregister insert to get us there.
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if (VecTy.getSizeInBits() != 128) {
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MachineInstr *ScalarToVector = emitScalarToVector(
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VecTy.getSizeInBits(), &AArch64::FPR128RegClass, VecReg, MIRBuilder);
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if (!ScalarToVector)
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return nullptr;
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InsertReg = ScalarToVector->getOperand(0).getReg();
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}
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MachineInstr *LaneCopyMI =
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MIRBuilder.buildInstr(CopyOpc, {*DstReg}, {InsertReg}).addImm(LaneIdx);
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constrainSelectedInstRegOperands(*LaneCopyMI, TII, TRI, RBI);
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// Make sure that we actually constrain the initial copy.
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RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);
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return LaneCopyMI;
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}
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bool AArch64InstructionSelector::selectExtractElt(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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assert(I.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT &&
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@ -1878,7 +1946,7 @@ bool AArch64InstructionSelector::selectExtractElt(
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const LLT NarrowTy = MRI.getType(DstReg);
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const unsigned SrcReg = I.getOperand(1).getReg();
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const LLT WideTy = MRI.getType(SrcReg);
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(void)WideTy;
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assert(WideTy.getSizeInBits() >= NarrowTy.getSizeInBits() &&
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"source register size too small!");
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assert(NarrowTy.isScalar() && "cannot extract vector into vector!");
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@ -1897,63 +1965,44 @@ bool AArch64InstructionSelector::selectExtractElt(
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if (!getConstantValueForReg(LaneIdxOp.getReg(), MRI, LaneIdx))
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return false;
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unsigned CopyOpc = 0;
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unsigned ExtractSubReg = 0;
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if (!getLaneCopyOpcode(CopyOpc, ExtractSubReg, NarrowTy.getSizeInBits())) {
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LLVM_DEBUG(
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dbgs() << "Couldn't determine lane copy opcode for instruction.\n");
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return false;
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}
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const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
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const TargetRegisterClass *DstRC =
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getRegClassForTypeOnBank(NarrowTy, DstRB, RBI, true);
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if (!DstRC) {
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LLVM_DEBUG(dbgs() << "Could not determine destination register class.\n");
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return false;
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}
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const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
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const TargetRegisterClass *SrcRC =
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getRegClassForTypeOnBank(WideTy, SrcRB, RBI, true);
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if (!SrcRC) {
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LLVM_DEBUG(dbgs() << "Could not determine source register class.\n");
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return false;
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}
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// The register that we're going to copy into.
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unsigned InsertReg = SrcReg;
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MachineIRBuilder MIRBuilder(I);
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// If the lane index is 0, we just use a subregister COPY.
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if (LaneIdx == 0) {
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unsigned CopyTo = I.getOperand(0).getReg();
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BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
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CopyTo)
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.addUse(SrcReg, 0, ExtractSubReg);
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RBI.constrainGenericRegister(CopyTo, *DstRC, MRI);
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I.eraseFromParent();
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return true;
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const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
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MachineInstr *Extract = emitExtractVectorElt(DstReg, DstRB, NarrowTy, SrcReg,
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LaneIdx, MIRBuilder);
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if (!Extract)
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return false;
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I.eraseFromParent();
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return true;
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}
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bool AArch64InstructionSelector::selectSplitVectorUnmerge(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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unsigned NumElts = I.getNumOperands() - 1;
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unsigned SrcReg = I.getOperand(NumElts).getReg();
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const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg());
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const LLT SrcTy = MRI.getType(SrcReg);
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assert(NarrowTy.isVector() && "Expected an unmerge into vectors");
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if (SrcTy.getSizeInBits() > 128) {
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LLVM_DEBUG(dbgs() << "Unexpected vector type for vec split unmerge");
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return false;
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}
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// Lane copies require 128-bit wide registers. If we're dealing with an
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// unpacked vector, then we need to move up to that width. Insert an implicit
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// def and a subregister insert to get us there.
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if (WideTy.getSizeInBits() != 128) {
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MachineInstr *ScalarToVector = emitScalarToVector(
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WideTy.getSizeInBits(), &AArch64::FPR128RegClass, SrcReg, MIRBuilder);
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if (!ScalarToVector)
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MachineIRBuilder MIB(I);
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// We implement a split vector operation by treating the sub-vectors as
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// scalars and extracting them.
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const RegisterBank &DstRB =
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*RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI);
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for (unsigned OpIdx = 0; OpIdx < NumElts; ++OpIdx) {
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unsigned Dst = I.getOperand(OpIdx).getReg();
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MachineInstr *Extract =
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emitExtractVectorElt(Dst, DstRB, NarrowTy, SrcReg, OpIdx, MIB);
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if (!Extract)
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return false;
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InsertReg = ScalarToVector->getOperand(0).getReg();
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}
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MachineInstr *LaneCopyMI =
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MIRBuilder.buildInstr(CopyOpc, {DstReg}, {InsertReg}).addImm(LaneIdx);
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constrainSelectedInstRegOperands(*LaneCopyMI, TII, TRI, RBI);
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// Make sure that we actually constrain the initial copy.
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RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
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I.eraseFromParent();
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return true;
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}
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@ -1984,11 +2033,8 @@ bool AArch64InstructionSelector::selectUnmergeValues(
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assert(WideTy.getSizeInBits() > NarrowTy.getSizeInBits() &&
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"source register size too small!");
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// TODO: Handle unmerging into vectors.
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if (!NarrowTy.isScalar()) {
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LLVM_DEBUG(dbgs() << "Vector-to-vector unmerges not supported yet.\n");
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return false;
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}
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if (!NarrowTy.isScalar())
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return selectSplitVectorUnmerge(I, MRI);
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// Choose a lane copy opcode and subregister based off of the size of the
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// vector's elements.
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@ -19,6 +19,14 @@
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ret <8 x half> %a
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}
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define <2 x float> @test_vecsplit_2v2s32_v4s32(<4 x float> %a) {
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ret <2 x float> undef
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}
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define <2 x half> @test_vecsplit_2v2s16_v4s16(<4 x half> %a) {
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ret <2 x half> undef
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}
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...
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---
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name: test_v2s64_unmerge
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@ -152,3 +160,51 @@ body: |
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_vecsplit_2v2s32_v4s32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1 (%ir-block.0):
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liveins: $q0
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; CHECK-LABEL: name: test_vecsplit_2v2s32_v4s32
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
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; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1
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; CHECK: $d0 = COPY [[COPY1]]
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; CHECK: $d1 = COPY [[CPYi64_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<2 x s32>), %2:fpr(<2 x s32>) = G_UNMERGE_VALUES %0(<4 x s32>)
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$d0 = COPY %1(<2 x s32>)
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$d1 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_vecsplit_2v2s16_v4s16
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1 (%ir-block.0):
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liveins: $d0
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; CHECK-LABEL: name: test_vecsplit_2v2s16_v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK: [[CPYi32_:%[0-9]+]]:fpr32 = CPYi32 [[INSERT_SUBREG]], 1
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; CHECK: $s0 = COPY [[COPY1]]
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; CHECK: $s1 = COPY [[CPYi32_]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<2 x s16>), %2:fpr(<2 x s16>) = G_UNMERGE_VALUES %0(<4 x s16>)
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$s0 = COPY %1(<2 x s16>)
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$s1 = COPY %2(<2 x s16>)
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RET_ReallyLR implicit $s0
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...
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