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Finish the incomplete 'd' inline asm constraint support for PPC by

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making sure we give it a register and mark it as a register constraint.

llvm-svn: 264340
This commit is contained in:
Eric Christopher 2016-03-24 21:04:52 +00:00
parent 0b5937f7d0
commit 6ddb84b162
2 changed files with 36 additions and 1 deletions
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5
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -10828,6 +10828,7 @@ PPCTargetLowering::getConstraintType(StringRef Constraint) const {
case 'b':
case 'r':
case 'f':
case 'd':
case 'v':
case 'y':
return C_RegisterClass;
@ -10919,6 +10920,10 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (VT == MVT::i64 && Subtarget.isPPC64())
return std::make_pair(0U, &PPC::G8RCRegClass);
return std::make_pair(0U, &PPC::GPRCRegClass);
// 'd' and 'f' constraints are both defined to be "the floating point
// registers", where one is for 32-bit and the other for 64-bit. We don't
// really care overly much here so just give them all the same reg classes.
case 'd':
case 'f':
if (VT == MVT::f32 || VT == MVT::i32)
return std::make_pair(0U, &PPC::F4RCRegClass);

32
test/CodeGen/PowerPC/asm-constraints.ll
View File

@ -37,7 +37,37 @@ entry:
ret void
}
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
; Function Attrs: nounwind
; Check that we accept the 'd' constraint.
; Generated from the following C code:
; int foo(double x) {
; int64_t result;
; __asm__ __volatile__("fctid %0, %1"
; : "=d"(result)
; : "d"(x)
; : /* No clobbers */);
; return result;
; }
define signext i32 @bar(double %x) #0 {
; CHECK-LABEL: @bar
; CHECK: fctid 0, 1
entry:
%x.addr = alloca double, align 8
%result = alloca i64, align 8
store double %x, double* %x.addr, align 8
%0 = load double, double* %x.addr, align 8
%1 = call i64 asm sideeffect "fctid $0, $1", "=d,d"(double %0) #1, !srcloc !1
store i64 %1, i64* %result, align 8
%2 = load i64, i64* %result, align 8
%conv = trunc i64 %2 to i32
ret i32 %conv
}
attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind }
!0 = !{i32 67, i32 91, i32 110, i32 126}
!1 = !{i32 84}