From 6e28c84a3a5740534ff76753c358a9170a683f7f Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 22 Apr 2020 16:33:11 +0100 Subject: [PATCH] [ARM] Replace arm vendor with none. NFC --- test/CodeGen/ARM/cmov_fp16.ll | 2 +- test/CodeGen/Thumb2/csel.ll | 2 +- test/CodeGen/Thumb2/fp16-stacksplot.mir | 2 +- test/CodeGen/Thumb2/lsll0.ll | 2 +- test/CodeGen/Thumb2/mve-abs.ll | 2 +- test/CodeGen/Thumb2/mve-be.ll | 2 +- test/CodeGen/Thumb2/mve-bitarith.ll | 2 +- test/CodeGen/Thumb2/mve-bitcasts.ll | 4 ++-- test/CodeGen/Thumb2/mve-bitreverse.ll | 2 +- test/CodeGen/Thumb2/mve-bswap.ll | 2 +- test/CodeGen/Thumb2/mve-ctlz.ll | 2 +- test/CodeGen/Thumb2/mve-ctpop.ll | 2 +- test/CodeGen/Thumb2/mve-cttz.ll | 2 +- test/CodeGen/Thumb2/mve-div-expand.ll | 4 ++-- test/CodeGen/Thumb2/mve-extractelt.ll | 2 +- test/CodeGen/Thumb2/mve-float16regloops.ll | 2 +- test/CodeGen/Thumb2/mve-float32regloops.ll | 2 +- test/CodeGen/Thumb2/mve-fma-loops.ll | 2 +- test/CodeGen/Thumb2/mve-fmas.ll | 6 +++--- test/CodeGen/Thumb2/mve-fmath.ll | 4 ++-- test/CodeGen/Thumb2/mve-fp-negabs.ll | 4 ++-- test/CodeGen/Thumb2/mve-frint.ll | 4 ++-- test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll | 2 +- test/CodeGen/Thumb2/mve-gather-ind16-unscaled.ll | 2 +- test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll | 2 +- test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll | 2 +- test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll | 2 +- test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll | 2 +- test/CodeGen/Thumb2/mve-gather-ptrs.ll | 2 +- test/CodeGen/Thumb2/mve-gather-scatter-opt.ll | 4 ++-- .../Thumb2/mve-gather-scatter-optimisation.ll | 2 +- test/CodeGen/Thumb2/mve-halving.ll | 2 +- .../CodeGen/Thumb2/mve-intrinsics/longshift-const.ll | 2 +- .../Thumb2/mve-intrinsics/longshift-demand.ll | 2 +- test/CodeGen/Thumb2/mve-ldst-offset.ll | 2 +- test/CodeGen/Thumb2/mve-ldst-postinc.ll | 2 +- test/CodeGen/Thumb2/mve-ldst-preinc.ll | 2 +- test/CodeGen/Thumb2/mve-ldst-regimm.ll | 2 +- test/CodeGen/Thumb2/mve-loadstore.ll | 2 +- test/CodeGen/Thumb2/mve-masked-ldst-offset.ll | 2 +- test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll | 2 +- test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll | 2 +- test/CodeGen/Thumb2/mve-masked-ldst.ll | 2 +- test/CodeGen/Thumb2/mve-masked-load.ll | 2 +- test/CodeGen/Thumb2/mve-masked-store.ll | 2 +- test/CodeGen/Thumb2/mve-minmax.ll | 4 ++-- test/CodeGen/Thumb2/mve-multivec-spill.ll | 2 +- test/CodeGen/Thumb2/mve-neg.ll | 2 +- test/CodeGen/Thumb2/mve-phireg.ll | 2 +- test/CodeGen/Thumb2/mve-postinc-distribute.ll | 2 +- test/CodeGen/Thumb2/mve-postinc-distribute.mir | 2 +- test/CodeGen/Thumb2/mve-postinc-lsr.ll | 2 +- test/CodeGen/Thumb2/mve-pred-and.ll | 2 +- test/CodeGen/Thumb2/mve-pred-bitcast.ll | 2 +- test/CodeGen/Thumb2/mve-pred-build-const.ll | 2 +- test/CodeGen/Thumb2/mve-pred-build-var.ll | 2 +- test/CodeGen/Thumb2/mve-pred-ext.ll | 2 +- test/CodeGen/Thumb2/mve-pred-loadstore.ll | 2 +- test/CodeGen/Thumb2/mve-pred-not.ll | 2 +- test/CodeGen/Thumb2/mve-pred-or.ll | 2 +- test/CodeGen/Thumb2/mve-pred-shuffle.ll | 2 +- test/CodeGen/Thumb2/mve-pred-spill.ll | 2 +- test/CodeGen/Thumb2/mve-pred-threshold.ll | 2 +- test/CodeGen/Thumb2/mve-pred-xor.ll | 2 +- test/CodeGen/Thumb2/mve-satmul-loops.ll | 2 +- test/CodeGen/Thumb2/mve-saturating-arith.ll | 2 +- test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll | 2 +- test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll | 2 +- test/CodeGen/Thumb2/mve-scatter-ind32-scaled.ll | 2 +- test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll | 2 +- test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll | 2 +- test/CodeGen/Thumb2/mve-scatter-ptrs.ll | 2 +- test/CodeGen/Thumb2/mve-sext.ll | 2 +- test/CodeGen/Thumb2/mve-shifts-scalar.ll | 2 +- test/CodeGen/Thumb2/mve-shifts.ll | 2 +- test/CodeGen/Thumb2/mve-shuffle.ll | 4 ++-- test/CodeGen/Thumb2/mve-shuffleext.ll | 2 +- test/CodeGen/Thumb2/mve-shufflemov.ll | 4 ++-- test/CodeGen/Thumb2/mve-simple-arith.ll | 4 ++-- test/CodeGen/Thumb2/mve-stack.ll | 2 +- test/CodeGen/Thumb2/mve-stacksplot.mir | 2 +- test/CodeGen/Thumb2/mve-vaddqr.ll | 2 +- test/CodeGen/Thumb2/mve-vaddv.ll | 2 +- test/CodeGen/Thumb2/mve-vcmp.ll | 2 +- test/CodeGen/Thumb2/mve-vcmpf.ll | 4 ++-- test/CodeGen/Thumb2/mve-vcmpfr.ll | 4 ++-- test/CodeGen/Thumb2/mve-vcmpfz.ll | 4 ++-- test/CodeGen/Thumb2/mve-vcmpr.ll | 2 +- test/CodeGen/Thumb2/mve-vcmpz.ll | 2 +- test/CodeGen/Thumb2/mve-vcvt.ll | 4 ++-- test/CodeGen/Thumb2/mve-vdup.ll | 4 ++-- test/CodeGen/Thumb2/mve-vecreduce-add.ll | 2 +- test/CodeGen/Thumb2/mve-vecreduce-fadd.ll | 4 ++-- test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll | 4 ++-- test/CodeGen/Thumb2/mve-vecreduce-fmul.ll | 4 ++-- test/CodeGen/Thumb2/mve-vecreduce-mla.ll | 2 +- test/CodeGen/Thumb2/mve-vector-spill.ll | 2 +- test/CodeGen/Thumb2/mve-vfma.ll | 2 +- test/CodeGen/Thumb2/mve-vhaddsub.ll | 2 +- test/CodeGen/Thumb2/mve-vld2-post.ll | 2 +- test/CodeGen/Thumb2/mve-vld2.ll | 2 +- test/CodeGen/Thumb2/mve-vld3.ll | 2 +- test/CodeGen/Thumb2/mve-vld4-post.ll | 2 +- test/CodeGen/Thumb2/mve-vld4.ll | 2 +- test/CodeGen/Thumb2/mve-vldst4.ll | 2 +- test/CodeGen/Thumb2/mve-vmaxv.ll | 2 +- test/CodeGen/Thumb2/mve-vmla.ll | 2 +- test/CodeGen/Thumb2/mve-vmovimm.ll | 4 ++-- test/CodeGen/Thumb2/mve-vmovn.ll | 2 +- test/CodeGen/Thumb2/mve-vmovnstore.ll | 2 +- test/CodeGen/Thumb2/mve-vmull-loop.ll | 2 +- test/CodeGen/Thumb2/mve-vmull.ll | 2 +- test/CodeGen/Thumb2/mve-vmulqr.ll | 2 +- test/CodeGen/Thumb2/mve-vmvnimm.ll | 4 ++-- test/CodeGen/Thumb2/mve-vpsel.ll | 2 +- test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir | 2 +- .../Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-2-blocks.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block-elses.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block-optnone.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-blocks.ll | 2 +- test/CodeGen/Thumb2/mve-vpt-optimisations.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-preuse.mir | 2 +- test/CodeGen/Thumb2/mve-vqmovn.ll | 2 +- test/CodeGen/Thumb2/mve-vst2-post.ll | 2 +- test/CodeGen/Thumb2/mve-vst2.ll | 2 +- test/CodeGen/Thumb2/mve-vst3.ll | 2 +- test/CodeGen/Thumb2/mve-vst4-post.ll | 2 +- test/CodeGen/Thumb2/mve-vst4.ll | 2 +- test/CodeGen/Thumb2/mve-vsubqr.ll | 2 +- test/CodeGen/Thumb2/mve-widen-narrow.ll | 2 +- test/CodeGen/Thumb2/postinc-distribute.mir | 2 +- test/CodeGen/Thumb2/vqabs.ll | 2 +- test/CodeGen/Thumb2/vqneg.ll | 2 +- test/MC/ARM/vscclrm-asm.s | 2 +- .../CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll | 2 +- test/Transforms/CodeGenPrepare/ARM/sinkchain.ll | 2 +- test/Transforms/HardwareLoops/ARM/calls-codegen.ll | 4 ++-- test/Transforms/HardwareLoops/ARM/calls.ll | 12 ++++++------ test/Transforms/HardwareLoops/ARM/counter.ll | 2 +- test/Transforms/HardwareLoops/ARM/do-rem.ll | 2 +- test/Transforms/HardwareLoops/ARM/fp-emulation.ll | 4 ++-- test/Transforms/HardwareLoops/ARM/simple-do.ll | 6 +++--- test/Transforms/HardwareLoops/ARM/structure.ll | 6 +++--- test/Transforms/LoopVectorize/ARM/mve-reduce.ll | 2 +- test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll | 2 +- test/Transforms/LoopVectorize/ARM/mve-vldn.ll | 2 +- unittests/Target/ARM/MachineInstrTest.cpp | 10 +++++----- 154 files changed, 191 insertions(+), 191 deletions(-) diff --git a/test/CodeGen/ARM/cmov_fp16.ll b/test/CodeGen/ARM/cmov_fp16.ll index 925fed58281..2c368d1a41b 100644 --- a/test/CodeGen/ARM/cmov_fp16.ll +++ b/test/CodeGen/ARM/cmov_fp16.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes CHECK-THUMB,CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes CHECK-THUMB,CHECK ; RUN: llc -mtriple=armv8.2a-arm-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes CHECK-ARM,CHECK define i32 @test_ne(i32 %x, i32 %y, i32 %a, i32 %b) { diff --git a/test/CodeGen/Thumb2/csel.ll b/test/CodeGen/Thumb2/csel.ll index 4ff2fe512e0..f2cf3e839a8 100644 --- a/test/CodeGen/Thumb2/csel.ll +++ b/test/CodeGen/Thumb2/csel.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -verify-machineinstrs -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi %s -verify-machineinstrs -o - | FileCheck %s define i32 @csinc_const_65(i32 %a) { ; CHECK-LABEL: csinc_const_65: diff --git a/test/CodeGen/Thumb2/fp16-stacksplot.mir b/test/CodeGen/Thumb2/fp16-stacksplot.mir index 1e87efa0847..687c64d9ebf 100644 --- a/test/CodeGen/Thumb2/fp16-stacksplot.mir +++ b/test/CodeGen/Thumb2/fp16-stacksplot.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -o - %s -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+fullfp16 -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s +# RUN: llc -o - %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fullfp16 -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s --- name: func0 tracksRegLiveness: true diff --git a/test/CodeGen/Thumb2/lsll0.ll b/test/CodeGen/Thumb2/lsll0.ll index 58949cbbbf8..a56451f3612 100644 --- a/test/CodeGen/Thumb2/lsll0.ll +++ b/test/CodeGen/Thumb2/lsll0.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define void @_Z4loopPxS_iS_i(i64* %d) { ; CHECK-LABEL: _Z4loopPxS_iS_i: diff --git a/test/CodeGen/Thumb2/mve-abs.ll b/test/CodeGen/Thumb2/mve-abs.ll index 90c9206dd93..29878063a8c 100644 --- a/test/CodeGen/Thumb2/mve-abs.ll +++ b/test/CodeGen/Thumb2/mve-abs.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @abs_v16i8(<16 x i8> %s1) { ; CHECK-LABEL: abs_v16i8: diff --git a/test/CodeGen/Thumb2/mve-be.ll b/test/CodeGen/Thumb2/mve-be.ll index 3db11f1e429..9dee871bf6a 100644 --- a/test/CodeGen/Thumb2/mve-be.ll +++ b/test/CodeGen/Thumb2/mve-be.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define void @load_load_add_store(<4 x i32> *%src1, <4 x i32> *%src2) { diff --git a/test/CodeGen/Thumb2/mve-bitarith.ll b/test/CodeGen/Thumb2/mve-bitarith.ll index 30981816922..e159e2df40e 100644 --- a/test/CodeGen/Thumb2/mve-bitarith.ll +++ b/test/CodeGen/Thumb2/mve-bitarith.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @and_int8_t(<16 x i8> %src1, <16 x i8> %src2) { ; CHECK-LABEL: and_int8_t: diff --git a/test/CodeGen/Thumb2/mve-bitcasts.ll b/test/CodeGen/Thumb2/mve-bitcasts.ll index bbb505abc8d..0c57cd4c02d 100644 --- a/test/CodeGen/Thumb2/mve-bitcasts.ll +++ b/test/CodeGen/Thumb2/mve-bitcasts.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <2 x i64> @bitcast_i64_i64(<2 x i64> %src) { ; CHECK-LABEL: bitcast_i64_i64: diff --git a/test/CodeGen/Thumb2/mve-bitreverse.ll b/test/CodeGen/Thumb2/mve-bitreverse.ll index 99f9506c3a9..6ba505978ff 100644 --- a/test/CodeGen/Thumb2/mve-bitreverse.ll +++ b/test/CodeGen/Thumb2/mve-bitreverse.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <2 x i64> @brv_2i64_t(<2 x i64> %src){ ; CHECK-LABEL: brv_2i64_t: diff --git a/test/CodeGen/Thumb2/mve-bswap.ll b/test/CodeGen/Thumb2/mve-bswap.ll index c7d3f844fd7..f1286983402 100644 --- a/test/CodeGen/Thumb2/mve-bswap.ll +++ b/test/CodeGen/Thumb2/mve-bswap.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @bswap_4i32_t(<4 x i32> %src){ ; CHECK-LABEL: bswap_4i32_t: diff --git a/test/CodeGen/Thumb2/mve-ctlz.ll b/test/CodeGen/Thumb2/mve-ctlz.ll index 5e866a1b0b8..9750b888804 100644 --- a/test/CodeGen/Thumb2/mve-ctlz.ll +++ b/test/CodeGen/Thumb2/mve-ctlz.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){ ; CHECK-LABEL: ctlz_2i64_0_t: diff --git a/test/CodeGen/Thumb2/mve-ctpop.ll b/test/CodeGen/Thumb2/mve-ctpop.ll index d6d215cc7ed..6a795c415d6 100644 --- a/test/CodeGen/Thumb2/mve-ctpop.ll +++ b/test/CodeGen/Thumb2/mve-ctpop.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autoenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){ ; CHECK-LABEL: ctpop_2i64_t: diff --git a/test/CodeGen/Thumb2/mve-cttz.ll b/test/CodeGen/Thumb2/mve-cttz.ll index 3a77883babf..e17107cf66c 100644 --- a/test/CodeGen/Thumb2/mve-cttz.ll +++ b/test/CodeGen/Thumb2/mve-cttz.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_0_t(<2 x i64> %src){ ; CHECK-LABEL: cttz_2i64_0_t: diff --git a/test/CodeGen/Thumb2/mve-div-expand.ll b/test/CodeGen/Thumb2/mve-div-expand.ll index 41e5a27d265..d72495b215b 100644 --- a/test/CodeGen/Thumb2/mve-div-expand.ll +++ b/test/CodeGen/Thumb2/mve-div-expand.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x i32> @udiv_i32(<4 x i32> %in1, <4 x i32> %in2) { ; CHECK-LABEL: udiv_i32: diff --git a/test/CodeGen/Thumb2/mve-extractelt.ll b/test/CodeGen/Thumb2/mve-extractelt.ll index e0f1e9468c5..f9359c83884 100644 --- a/test/CodeGen/Thumb2/mve-extractelt.ll +++ b/test/CodeGen/Thumb2/mve-extractelt.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc i32 @u8_explicit_extend(<16 x i8> %a) { ; CHECK-LABEL: u8_explicit_extend: diff --git a/test/CodeGen/Thumb2/mve-float16regloops.ll b/test/CodeGen/Thumb2/mve-float16regloops.ll index 38083b7edcc..17b0077c0e8 100644 --- a/test/CodeGen/Thumb2/mve-float16regloops.ll +++ b/test/CodeGen/Thumb2/mve-float16regloops.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc void @test_fadd(half* noalias nocapture readonly %A, half *%BB, half* noalias nocapture %C, i32 %n) { ; CHECK-LABEL: test_fadd: diff --git a/test/CodeGen/Thumb2/mve-float32regloops.ll b/test/CodeGen/Thumb2/mve-float32regloops.ll index e86d3606f27..da082719f45 100644 --- a/test/CodeGen/Thumb2/mve-float32regloops.ll +++ b/test/CodeGen/Thumb2/mve-float32regloops.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc void @test_fadd(float* noalias nocapture readonly %A, float %B, float* noalias nocapture %C, i32 %n) { ; CHECK-LABEL: test_fadd: diff --git a/test/CodeGen/Thumb2/mve-fma-loops.ll b/test/CodeGen/Thumb2/mve-fma-loops.ll index 9438a0d3903..6d530b91754 100644 --- a/test/CodeGen/Thumb2/mve-fma-loops.ll +++ b/test/CodeGen/Thumb2/mve-fma-loops.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs -disable-mve-tail-predication=false %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs -disable-mve-tail-predication=false %s -o - | FileCheck %s define arm_aapcs_vfpcc void @fmas1(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { ; CHECK-LABEL: fmas1: diff --git a/test/CodeGen/Thumb2/mve-fmas.ll b/test/CodeGen/Thumb2/mve-fmas.ll index 789e06a0114..ecfdbc71457 100644 --- a/test/CodeGen/Thumb2/mve-fmas.ll +++ b/test/CodeGen/Thumb2/mve-fmas.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi, -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-FP -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi, -mattr=+mve.fp -fp-contract=fast -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-VMLA -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi, -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-FP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi, -mattr=+mve.fp -fp-contract=fast -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-VMLA +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE define arm_aapcs_vfpcc <8 x half> @vfma16_v1(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) { ; CHECK-MVE-FP-LABEL: vfma16_v1: diff --git a/test/CodeGen/Thumb2/mve-fmath.ll b/test/CodeGen/Thumb2/mve-fmath.ll index 6fece1ac0c7..d93f31c9e21 100644 --- a/test/CodeGen/Thumb2/mve-fmath.ll +++ b/test/CodeGen/Thumb2/mve-fmath.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x float> @sqrt_float32_t(<4 x float> %src) { ; CHECK-LABEL: sqrt_float32_t: diff --git a/test/CodeGen/Thumb2/mve-fp-negabs.ll b/test/CodeGen/Thumb2/mve-fp-negabs.ll index 9b295d3117a..50d8752176a 100644 --- a/test/CodeGen/Thumb2/mve-fp-negabs.ll +++ b/test/CodeGen/Thumb2/mve-fp-negabs.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) { ; CHECK-MVE-LABEL: fneg_float16_t: diff --git a/test/CodeGen/Thumb2/mve-frint.ll b/test/CodeGen/Thumb2/mve-frint.ll index 6d936a375dd..410c4f18bd0 100644 --- a/test/CodeGen/Thumb2/mve-frint.ll +++ b/test/CodeGen/Thumb2/mve-frint.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x float> @fceil_float32_t(<4 x float> %src) { ; CHECK-MVE-LABEL: fceil_float32_t: diff --git a/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll b/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll index 948f030a84d..30ce13b8507 100644 --- a/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll +++ b/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16(i16* %base, <8 x i16>* %offptr) { ; CHECK-LABEL: scaled_v8i16_i16: diff --git a/test/CodeGen/Thumb2/mve-gather-ind16-unscaled.ll b/test/CodeGen/Thumb2/mve-gather-ind16-unscaled.ll index ee266761455..7e96a213e5c 100644 --- a/test/CodeGen/Thumb2/mve-gather-ind16-unscaled.ll +++ b/test/CodeGen/Thumb2/mve-gather-ind16-unscaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s define arm_aapcs_vfpcc <8 x i16> @zext_unscaled_i8_i16(i8* %base, <8 x i16>* %offptr) { ; CHECK-LABEL: zext_unscaled_i8_i16: diff --git a/test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll b/test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll index 0cbfb8961eb..c674ffbf51b 100644 --- a/test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll +++ b/test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @zext_scaled_i16_i32(i16* %base, <4 x i32>* %offptr) { ; CHECK-LABEL: zext_scaled_i16_i32: diff --git a/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll b/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll index ac365ab23f7..1b6acbd8338 100644 --- a/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll +++ b/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @zext_unscaled_i8_i32(i8* %base, <4 x i32>* %offptr) { ; CHECK-LABEL: zext_unscaled_i8_i32: diff --git a/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll b/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll index deb3be28ddb..60bffc5a31d 100644 --- a/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll +++ b/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @unscaled_v16i8_i8(i8* %base, <16 x i8>* %offptr) { ; CHECK-LABEL: unscaled_v16i8_i8: diff --git a/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll b/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll index a86a89972cf..22f6cd6bc3d 100644 --- a/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll +++ b/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt --mve-gather-scatter-lowering -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -S -o 2>/dev/null - | FileCheck %s +; RUN: opt --mve-gather-scatter-lowering -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -S -o 2>/dev/null - | FileCheck %s define arm_aapcs_vfpcc void @push_out_add_sub_block(i32* noalias nocapture readonly %data, i32* noalias nocapture %dst, i32 %n.vec) { ; CHECK-LABEL: @push_out_add_sub_block( diff --git a/test/CodeGen/Thumb2/mve-gather-ptrs.ll b/test/CodeGen/Thumb2/mve-gather-ptrs.ll index c44668c7f5b..78e3ced1ceb 100644 --- a/test/CodeGen/Thumb2/mve-gather-ptrs.ll +++ b/test/CodeGen/Thumb2/mve-gather-ptrs.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -enable-arm-maskedgatscat %s -o - | FileCheck %s ; i32 diff --git a/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll b/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll index c9bb6660c85..7f4bdbb0f93 100644 --- a/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll +++ b/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o 2>/dev/null - | FileCheck --check-prefix NOGATSCAT %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=-mve -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck --check-prefix NOMVE %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o 2>/dev/null - | FileCheck --check-prefix NOGATSCAT %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=-mve -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck --check-prefix NOMVE %s define arm_aapcs_vfpcc <4 x i32> @unscaled_i32_i32_gather(i8* %base, <4 x i32>* %offptr) { ; NOGATSCAT-LABEL: unscaled_i32_i32_gather: diff --git a/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll b/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll index e7069676110..e3c8761722f 100644 --- a/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll +++ b/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s !0 = !{i32 1, !"wchar_size", i32 4} !1 = !{i32 1, !"min_enum_size", i32 4} diff --git a/test/CodeGen/Thumb2/mve-halving.ll b/test/CodeGen/Thumb2/mve-halving.ll index 08877d4fc25..69e714f8eb5 100644 --- a/test/CodeGen/Thumb2/mve-halving.ll +++ b/test/CodeGen/Thumb2/mve-halving.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @vhadds_v16i8(<16 x i8> %x, <16 x i8> %y) { ; CHECK-LABEL: vhadds_v16i8: diff --git a/test/CodeGen/Thumb2/mve-intrinsics/longshift-const.ll b/test/CodeGen/Thumb2/mve-intrinsics/longshift-const.ll index 2a6a4a36c92..1fbf4e6734f 100644 --- a/test/CodeGen/Thumb2/mve-intrinsics/longshift-const.ll +++ b/test/CodeGen/Thumb2/mve-intrinsics/longshift-const.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s declare {i32, i32} @llvm.arm.mve.asrl(i32, i32, i32) declare {i32, i32} @llvm.arm.mve.lsll(i32, i32, i32) diff --git a/test/CodeGen/Thumb2/mve-intrinsics/longshift-demand.ll b/test/CodeGen/Thumb2/mve-intrinsics/longshift-demand.ll index df945cd7d50..03da1126950 100644 --- a/test/CodeGen/Thumb2/mve-intrinsics/longshift-demand.ll +++ b/test/CodeGen/Thumb2/mve-intrinsics/longshift-demand.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s declare {i32, i32} @llvm.arm.mve.asrl(i32, i32, i32) declare {i32, i32} @llvm.arm.mve.lsll(i32, i32, i32) diff --git a/test/CodeGen/Thumb2/mve-ldst-offset.ll b/test/CodeGen/Thumb2/mve-ldst-offset.ll index 54befb26d16..b81ee354140 100644 --- a/test/CodeGen/Thumb2/mve-ldst-offset.ll +++ b/test/CodeGen/Thumb2/mve-ldst-offset.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define i8* @ldrwu32_4(i8* %x, i8* %y) { diff --git a/test/CodeGen/Thumb2/mve-ldst-postinc.ll b/test/CodeGen/Thumb2/mve-ldst-postinc.ll index 3d0634c0ca8..486ee969248 100644 --- a/test/CodeGen/Thumb2/mve-ldst-postinc.ll +++ b/test/CodeGen/Thumb2/mve-ldst-postinc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define i8* @ldrwu32_4(i8* %x, i8* %y) { diff --git a/test/CodeGen/Thumb2/mve-ldst-preinc.ll b/test/CodeGen/Thumb2/mve-ldst-preinc.ll index bf732c628ee..edcadf30426 100644 --- a/test/CodeGen/Thumb2/mve-ldst-preinc.ll +++ b/test/CodeGen/Thumb2/mve-ldst-preinc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define i8* @ldrwu32_4(i8* %x, i8* %y) { diff --git a/test/CodeGen/Thumb2/mve-ldst-regimm.ll b/test/CodeGen/Thumb2/mve-ldst-regimm.ll index e57708d1ea3..43564017f35 100644 --- a/test/CodeGen/Thumb2/mve-ldst-regimm.ll +++ b/test/CodeGen/Thumb2/mve-ldst-regimm.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s %struct.s_int8_t = type { [16 x i8], [16 x i8] } %struct.s_int16_t = type { [8 x i16], [8 x i16] } diff --git a/test/CodeGen/Thumb2/mve-loadstore.ll b/test/CodeGen/Thumb2/mve-loadstore.ll index 20fce95d6d9..3e0c345932d 100644 --- a/test/CodeGen/Thumb2/mve-loadstore.ll +++ b/test/CodeGen/Thumb2/mve-loadstore.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define arm_aapcs_vfpcc <4 x i32> @load_4xi32_a4(<4 x i32>* %vp) { diff --git a/test/CodeGen/Thumb2/mve-masked-ldst-offset.ll b/test/CodeGen/Thumb2/mve-masked-ldst-offset.ll index 5e2e85017e2..96181701f3b 100644 --- a/test/CodeGen/Thumb2/mve-masked-ldst-offset.ll +++ b/test/CodeGen/Thumb2/mve-masked-ldst-offset.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define i8* @ldrwu32_4(i8* %x, i8* %y, <4 x i32> *%m) { diff --git a/test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll b/test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll index f80372209e3..2b84d1b09ee 100644 --- a/test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll +++ b/test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define i8* @ldrwu32_4(i8* %x, i8* %y, <4 x i32> *%m) { diff --git a/test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll b/test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll index 424e16d22dc..bb671ed57e8 100644 --- a/test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll +++ b/test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define i8* @ldrwu32_4(i8* %x, i8* %y, <4 x i32> *%m) { diff --git a/test/CodeGen/Thumb2/mve-masked-ldst.ll b/test/CodeGen/Thumb2/mve-masked-ldst.ll index 3814b0b2766..d1829f70540 100644 --- a/test/CodeGen/Thumb2/mve-masked-ldst.ll +++ b/test/CodeGen/Thumb2/mve-masked-ldst.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define void @foo_v4i32_v4i32(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i32> *%src) { diff --git a/test/CodeGen/Thumb2/mve-masked-load.ll b/test/CodeGen/Thumb2/mve-masked-load.ll index ca51edb92a2..2c941d42a4b 100644 --- a/test/CodeGen/Thumb2/mve-masked-load.ll +++ b/test/CodeGen/Thumb2/mve-masked-load.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define arm_aapcs_vfpcc <4 x i32> @masked_v4i32_align4_zero(<4 x i32> *%dest, <4 x i32> %a) { diff --git a/test/CodeGen/Thumb2/mve-masked-store.ll b/test/CodeGen/Thumb2/mve-masked-store.ll index 215fe12334e..018c87a87b9 100644 --- a/test/CodeGen/Thumb2/mve-masked-store.ll +++ b/test/CodeGen/Thumb2/mve-masked-store.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define arm_aapcs_vfpcc void @masked_v4i32(<4 x i32> *%dest, <4 x i32> %a) { diff --git a/test/CodeGen/Thumb2/mve-minmax.ll b/test/CodeGen/Thumb2/mve-minmax.ll index 14b1f466bf6..c533216127b 100644 --- a/test/CodeGen/Thumb2/mve-minmax.ll +++ b/test/CodeGen/Thumb2/mve-minmax.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <16 x i8> @smin_v16i8(<16 x i8> %s1, <16 x i8> %s2) { ; CHECK-LABEL: smin_v16i8: diff --git a/test/CodeGen/Thumb2/mve-multivec-spill.ll b/test/CodeGen/Thumb2/mve-multivec-spill.ll index 6ff6d718ed7..a24637870b3 100644 --- a/test/CodeGen/Thumb2/mve-multivec-spill.ll +++ b/test/CodeGen/Thumb2/mve-multivec-spill.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -O3 -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -O3 -mattr=+mve %s -o - | FileCheck %s declare void @external_function() diff --git a/test/CodeGen/Thumb2/mve-neg.ll b/test/CodeGen/Thumb2/mve-neg.ll index 602ce3d5f9b..2d8d0f4ac51 100644 --- a/test/CodeGen/Thumb2/mve-neg.ll +++ b/test/CodeGen/Thumb2/mve-neg.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @neg_v16i8(<16 x i8> %s1) { ; CHECK-LABEL: neg_v16i8: diff --git a/test/CodeGen/Thumb2/mve-phireg.ll b/test/CodeGen/Thumb2/mve-phireg.ll index bc2ef68a8eb..e7d6a7323bc 100644 --- a/test/CodeGen/Thumb2/mve-phireg.ll +++ b/test/CodeGen/Thumb2/mve-phireg.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s ; verify-machineinstrs previously caught the incorrect use of QPR in the stack reloads. diff --git a/test/CodeGen/Thumb2/mve-postinc-distribute.ll b/test/CodeGen/Thumb2/mve-postinc-distribute.ll index 5be3f722a0e..fe9e7d197ca 100644 --- a/test/CodeGen/Thumb2/mve-postinc-distribute.ll +++ b/test/CodeGen/Thumb2/mve-postinc-distribute.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s ; Check some loop postinc's for properly distributed post-incs diff --git a/test/CodeGen/Thumb2/mve-postinc-distribute.mir b/test/CodeGen/Thumb2/mve-postinc-distribute.mir index d69037a952e..5fc89549ec9 100644 --- a/test/CodeGen/Thumb2/mve-postinc-distribute.mir +++ b/test/CodeGen/Thumb2/mve-postinc-distribute.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s --- | define i32* @MVE_VLDRWU32(i32* %x) { unreachable } diff --git a/test/CodeGen/Thumb2/mve-postinc-lsr.ll b/test/CodeGen/Thumb2/mve-postinc-lsr.ll index 789b6604b48..a9c9bb9cba6 100644 --- a/test/CodeGen/Thumb2/mve-postinc-lsr.ll +++ b/test/CodeGen/Thumb2/mve-postinc-lsr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s ; Check some LSR loop postinc diff --git a/test/CodeGen/Thumb2/mve-pred-and.ll b/test/CodeGen/Thumb2/mve-pred-and.ll index 4567f60b4ba..9848a56b9f3 100644 --- a/test/CodeGen/Thumb2/mve-pred-and.ll +++ b/test/CodeGen/Thumb2/mve-pred-and.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: cmpeqz_v4i1: diff --git a/test/CodeGen/Thumb2/mve-pred-bitcast.ll b/test/CodeGen/Thumb2/mve-pred-bitcast.ll index 61a78eb722e..955f48184c3 100644 --- a/test/CodeGen/Thumb2/mve-pred-bitcast.ll +++ b/test/CodeGen/Thumb2/mve-pred-bitcast.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define arm_aapcs_vfpcc <4 x i32> @bitcast_to_v4i1(i4 %b, <4 x i32> %a) { diff --git a/test/CodeGen/Thumb2/mve-pred-build-const.ll b/test/CodeGen/Thumb2/mve-pred-build-const.ll index 959b162add3..86634db14b3 100644 --- a/test/CodeGen/Thumb2/mve-pred-build-const.ll +++ b/test/CodeGen/Thumb2/mve-pred-build-const.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @build_true_v4i1(<4 x i32> %a, <4 x i32> %b) { diff --git a/test/CodeGen/Thumb2/mve-pred-build-var.ll b/test/CodeGen/Thumb2/mve-pred-build-var.ll index ae2ee6a94e1..4d0568a675b 100644 --- a/test/CodeGen/Thumb2/mve-pred-build-var.ll +++ b/test/CodeGen/Thumb2/mve-pred-build-var.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @build_var0_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) { diff --git a/test/CodeGen/Thumb2/mve-pred-ext.ll b/test/CodeGen/Thumb2/mve-pred-ext.ll index 99bd003c8fc..b88576a22cc 100644 --- a/test/CodeGen/Thumb2/mve-pred-ext.ll +++ b/test/CodeGen/Thumb2/mve-pred-ext.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @sext_v4i1_v4i32(<4 x i32> %src) { ; CHECK-LABEL: sext_v4i1_v4i32: diff --git a/test/CodeGen/Thumb2/mve-pred-loadstore.ll b/test/CodeGen/Thumb2/mve-pred-loadstore.ll index 21af261170e..0dbbe3f663c 100644 --- a/test/CodeGen/Thumb2/mve-pred-loadstore.ll +++ b/test/CodeGen/Thumb2/mve-pred-loadstore.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define arm_aapcs_vfpcc <4 x i32> @load_v4i1(<4 x i1> *%src, <4 x i32> %a) { diff --git a/test/CodeGen/Thumb2/mve-pred-not.ll b/test/CodeGen/Thumb2/mve-pred-not.ll index a16fce870cb..e4f9b1e1bd5 100644 --- a/test/CodeGen/Thumb2/mve-pred-not.ll +++ b/test/CodeGen/Thumb2/mve-pred-not.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: cmpeqz_v4i1: diff --git a/test/CodeGen/Thumb2/mve-pred-or.ll b/test/CodeGen/Thumb2/mve-pred-or.ll index 26ff81c6f39..4e9e074083f 100644 --- a/test/CodeGen/Thumb2/mve-pred-or.ll +++ b/test/CodeGen/Thumb2/mve-pred-or.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: cmpeqz_v4i1: diff --git a/test/CodeGen/Thumb2/mve-pred-shuffle.ll b/test/CodeGen/Thumb2/mve-pred-shuffle.ll index 1b00b708db3..d325138a0b8 100644 --- a/test/CodeGen/Thumb2/mve-pred-shuffle.ll +++ b/test/CodeGen/Thumb2/mve-pred-shuffle.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define <4 x i32> @shuffle1_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: shuffle1_v4i32: diff --git a/test/CodeGen/Thumb2/mve-pred-spill.ll b/test/CodeGen/Thumb2/mve-pred-spill.ll index ccbe5033514..6ae083dd297 100644 --- a/test/CodeGen/Thumb2/mve-pred-spill.ll +++ b/test/CodeGen/Thumb2/mve-pred-spill.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE declare arm_aapcs_vfpcc <4 x i32> @ext_i32(<4 x i32> %c) diff --git a/test/CodeGen/Thumb2/mve-pred-threshold.ll b/test/CodeGen/Thumb2/mve-pred-threshold.ll index df211f1efeb..0ba0e8a6c40 100644 --- a/test/CodeGen/Thumb2/mve-pred-threshold.ll +++ b/test/CodeGen/Thumb2/mve-pred-threshold.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc void @thres_i32(i32* %data, i16 zeroext %N, i32 %T) { ; CHECK-LABEL: thres_i32: diff --git a/test/CodeGen/Thumb2/mve-pred-xor.ll b/test/CodeGen/Thumb2/mve-pred-xor.ll index 07821a29e54..f92a4bd958f 100644 --- a/test/CodeGen/Thumb2/mve-pred-xor.ll +++ b/test/CodeGen/Thumb2/mve-pred-xor.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: cmpeqz_v4i1: diff --git a/test/CodeGen/Thumb2/mve-satmul-loops.ll b/test/CodeGen/Thumb2/mve-satmul-loops.ll index d01ef0095a6..d89c2401464 100644 --- a/test/CodeGen/Thumb2/mve-satmul-loops.ll +++ b/test/CodeGen/Thumb2/mve-satmul-loops.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc void @ssatmul_s_q31(i32* nocapture readonly %pSrcA, i32* nocapture readonly %pSrcB, i32* noalias nocapture %pDst, i32 %N) { ; CHECK-LABEL: ssatmul_s_q31: diff --git a/test/CodeGen/Thumb2/mve-saturating-arith.ll b/test/CodeGen/Thumb2/mve-saturating-arith.ll index 3610c2a6565..8457a3ab7a1 100644 --- a/test/CodeGen/Thumb2/mve-saturating-arith.ll +++ b/test/CodeGen/Thumb2/mve-saturating-arith.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @sadd_int8_t(<16 x i8> %src1, <16 x i8> %src2) { ; CHECK-LABEL: sadd_int8_t: diff --git a/test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll b/test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll index 82f357d28a6..2d9e2047e08 100644 --- a/test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll +++ b/test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s ; VLDRH.16 Qd, [base, offs, uxtw #1] define arm_aapcs_vfpcc void @scaled_v8i16_i16(i16* %base, <8 x i16>* %offptr, <8 x i16> %input) { diff --git a/test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll b/test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll index 156bf982695..0993a61912a 100644 --- a/test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll +++ b/test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s ; VLDRB.u16 Qd, [base, offs] define arm_aapcs_vfpcc void @ext_unscaled_i8_i16(i8* %base, <8 x i16>* %offptr, <8 x i16> %input) { diff --git a/test/CodeGen/Thumb2/mve-scatter-ind32-scaled.ll b/test/CodeGen/Thumb2/mve-scatter-ind32-scaled.ll index 8dc00bcbd76..25a9cea5f5b 100644 --- a/test/CodeGen/Thumb2/mve-scatter-ind32-scaled.ll +++ b/test/CodeGen/Thumb2/mve-scatter-ind32-scaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s ; VLDRH.u32 Qd, [base, offs, #uxtw #1] define arm_aapcs_vfpcc void @ext_scaled_i16_i32(i16* %base, <4 x i32>* %offptr, <4 x i32> %input) { diff --git a/test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll b/test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll index 48c7b547e1b..a4ec18a2e2b 100644 --- a/test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll +++ b/test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s ; VLDRB.u32 Qd, [base, offs] define arm_aapcs_vfpcc void @ext_unscaled_i8_i32(i8* %base, <4 x i32>* %offptr, <4 x i32> %input) { diff --git a/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll b/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll index 878765c0a86..d84066cdc5b 100644 --- a/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll +++ b/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s ; VLDRB.8 define arm_aapcs_vfpcc void @unscaled_v16i8_i8(i8* %base, <16 x i8>* %offptr, <16 x i8> %input) { diff --git a/test/CodeGen/Thumb2/mve-scatter-ptrs.ll b/test/CodeGen/Thumb2/mve-scatter-ptrs.ll index a317bcd0745..11aaba9b552 100644 --- a/test/CodeGen/Thumb2/mve-scatter-ptrs.ll +++ b/test/CodeGen/Thumb2/mve-scatter-ptrs.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -enable-arm-maskedgatscat %s -o - | FileCheck %s ; i32 diff --git a/test/CodeGen/Thumb2/mve-sext.ll b/test/CodeGen/Thumb2/mve-sext.ll index f351e6dc01f..26f524d7aed 100644 --- a/test/CodeGen/Thumb2/mve-sext.ll +++ b/test/CodeGen/Thumb2/mve-sext.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @sext_v4i32_v4i32_v4i1(<4 x i32> %m) { ; CHECK-LABEL: sext_v4i32_v4i32_v4i1: diff --git a/test/CodeGen/Thumb2/mve-shifts-scalar.ll b/test/CodeGen/Thumb2/mve-shifts-scalar.ll index 2cc875fe0bc..33b3d0ed0b9 100644 --- a/test/CodeGen/Thumb2/mve-shifts-scalar.ll +++ b/test/CodeGen/Thumb2/mve-shifts-scalar.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s --verify-machineinstrs -o - | FileCheck %s +; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s --verify-machineinstrs -o - | FileCheck %s define dso_local arm_aapcs_vfpcc void @sink_shl_i32(i32* nocapture readonly %in, i32* noalias nocapture %out, i32 %shift, i32 %N) { ; CHECK-LABEL: sink_shl_i32: diff --git a/test/CodeGen/Thumb2/mve-shifts.ll b/test/CodeGen/Thumb2/mve-shifts.ll index 69e91a54c9a..8243e0df205 100644 --- a/test/CodeGen/Thumb2/mve-shifts.ll +++ b/test/CodeGen/Thumb2/mve-shifts.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @shl_qq_int8_t(<16 x i8> %src1, <16 x i8> %src2) { ; CHECK-LABEL: shl_qq_int8_t: diff --git a/test/CodeGen/Thumb2/mve-shuffle.ll b/test/CodeGen/Thumb2/mve-shuffle.ll index 2f6541b7be1..ce9abf80b9d 100644 --- a/test/CodeGen/Thumb2/mve-shuffle.ll +++ b/test/CodeGen/Thumb2/mve-shuffle.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x i32> @shuffle1_i32(<4 x i32> %src) { ; CHECK-LABEL: shuffle1_i32: diff --git a/test/CodeGen/Thumb2/mve-shuffleext.ll b/test/CodeGen/Thumb2/mve-shuffleext.ll index bd4cf69e7a8..c1a306a9271 100644 --- a/test/CodeGen/Thumb2/mve-shuffleext.ll +++ b/test/CodeGen/Thumb2/mve-shuffleext.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK define arm_aapcs_vfpcc <4 x i32> @sext_0246(<8 x i16> %src) { ; CHECK-LABEL: sext_0246: diff --git a/test/CodeGen/Thumb2/mve-shufflemov.ll b/test/CodeGen/Thumb2/mve-shufflemov.ll index 164d42f1515..4bde0e4d14d 100644 --- a/test/CodeGen/Thumb2/mve-shufflemov.ll +++ b/test/CodeGen/Thumb2/mve-shufflemov.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s ; i16 diff --git a/test/CodeGen/Thumb2/mve-simple-arith.ll b/test/CodeGen/Thumb2/mve-simple-arith.ll index 92b6ae5337f..dc04c5e7583 100644 --- a/test/CodeGen/Thumb2/mve-simple-arith.ll +++ b/test/CodeGen/Thumb2/mve-simple-arith.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <16 x i8> @add_int8_t(<16 x i8> %src1, <16 x i8> %src2) { ; CHECK-LABEL: add_int8_t: diff --git a/test/CodeGen/Thumb2/mve-stack.ll b/test/CodeGen/Thumb2/mve-stack.ll index 41cc1162ee9..ea272e19b23 100644 --- a/test/CodeGen/Thumb2/mve-stack.ll +++ b/test/CodeGen/Thumb2/mve-stack.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc void @vstrw32() { ; CHECK-LABEL: vstrw32: diff --git a/test/CodeGen/Thumb2/mve-stacksplot.mir b/test/CodeGen/Thumb2/mve-stacksplot.mir index f101783d7f0..a2c3bdc894e 100644 --- a/test/CodeGen/Thumb2/mve-stacksplot.mir +++ b/test/CodeGen/Thumb2/mve-stacksplot.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -o - %s -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s +# RUN: llc -o - %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s --- name: func0 tracksRegLiveness: true diff --git a/test/CodeGen/Thumb2/mve-vaddqr.ll b/test/CodeGen/Thumb2/mve-vaddqr.ll index dd97bd52dfd..da07cd67694 100644 --- a/test/CodeGen/Thumb2/mve-vaddqr.ll +++ b/test/CodeGen/Thumb2/mve-vaddqr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vaddqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: vaddqr_v4i32: diff --git a/test/CodeGen/Thumb2/mve-vaddv.ll b/test/CodeGen/Thumb2/mve-vaddv.ll index 1244fc7716b..e3f236bedc0 100644 --- a/test/CodeGen/Thumb2/mve-vaddv.ll +++ b/test/CodeGen/Thumb2/mve-vaddv.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s declare i64 @llvm.experimental.vector.reduce.add.i64.v2i64(<2 x i64>) declare i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32>) diff --git a/test/CodeGen/Thumb2/mve-vcmp.ll b/test/CodeGen/Thumb2/mve-vcmp.ll index 87f0e66fe30..a40beb4b0eb 100644 --- a/test/CodeGen/Thumb2/mve-vcmp.ll +++ b/test/CodeGen/Thumb2/mve-vcmp.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vcmp_eq_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: vcmp_eq_v4i32: diff --git a/test/CodeGen/Thumb2/mve-vcmpf.ll b/test/CodeGen/Thumb2/mve-vcmpf.ll index 9e793caac3d..7c60eeadbfb 100644 --- a/test/CodeGen/Thumb2/mve-vcmpf.ll +++ b/test/CodeGen/Thumb2/mve-vcmpf.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_oeq_v4f32: diff --git a/test/CodeGen/Thumb2/mve-vcmpfr.ll b/test/CodeGen/Thumb2/mve-vcmpfr.ll index c9325c28289..1c6c0ff9c2d 100644 --- a/test/CodeGen/Thumb2/mve-vcmpfr.ll +++ b/test/CodeGen/Thumb2/mve-vcmpfr.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_oeq_v4f32: diff --git a/test/CodeGen/Thumb2/mve-vcmpfz.ll b/test/CodeGen/Thumb2/mve-vcmpfz.ll index b6c28c3e101..20837421e97 100644 --- a/test/CodeGen/Thumb2/mve-vcmpfz.ll +++ b/test/CodeGen/Thumb2/mve-vcmpfz.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_oeq_v4f32: diff --git a/test/CodeGen/Thumb2/mve-vcmpr.ll b/test/CodeGen/Thumb2/mve-vcmpr.ll index c832c241e67..06361d95212 100644 --- a/test/CodeGen/Thumb2/mve-vcmpr.ll +++ b/test/CodeGen/Thumb2/mve-vcmpr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vcmp_eq_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: vcmp_eq_v4i32: diff --git a/test/CodeGen/Thumb2/mve-vcmpz.ll b/test/CodeGen/Thumb2/mve-vcmpz.ll index 6d08abc7230..e9b71749423 100644 --- a/test/CodeGen/Thumb2/mve-vcmpz.ll +++ b/test/CodeGen/Thumb2/mve-vcmpz.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vcmp_eqz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: vcmp_eqz_v4i32: diff --git a/test/CodeGen/Thumb2/mve-vcvt.ll b/test/CodeGen/Thumb2/mve-vcvt.ll index a2d8b582ad4..0cfe5cc80c1 100644 --- a/test/CodeGen/Thumb2/mve-vcvt.ll +++ b/test/CodeGen/Thumb2/mve-vcvt.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x float> @foo_float_int32(<4 x i32> %src) { ; CHECK-MVE-LABEL: foo_float_int32: diff --git a/test/CodeGen/Thumb2/mve-vdup.ll b/test/CodeGen/Thumb2/mve-vdup.ll index 829319ba7c0..f855b121590 100644 --- a/test/CodeGen/Thumb2/mve-vdup.ll +++ b/test/CodeGen/Thumb2/mve-vdup.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vdup_i32(i32 %src) { ; CHECK-LABEL: vdup_i32: diff --git a/test/CodeGen/Thumb2/mve-vecreduce-add.ll b/test/CodeGen/Thumb2/mve-vecreduce-add.ll index 7ea29277cc4..2f483b391c1 100644 --- a/test/CodeGen/Thumb2/mve-vecreduce-add.ll +++ b/test/CodeGen/Thumb2/mve-vecreduce-add.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x) { ; CHECK-LABEL: add_v4i32_v4i32: diff --git a/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll b/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll index 9d02a1c817c..d8d40e5b518 100644 --- a/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll +++ b/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP define arm_aapcs_vfpcc float @fadd_v2f32(<2 x float> %x, float %y) { ; CHECK-LABEL: fadd_v2f32: diff --git a/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll b/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll index 0b6f18d28d4..a2ab4af918b 100644 --- a/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll +++ b/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP ; FIXME minnum nonan X, +Inf -> X ? define arm_aapcs_vfpcc float @fmin_v2f32(<2 x float> %x) { diff --git a/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll b/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll index 1f98979d480..e4ac03e9b3c 100644 --- a/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll +++ b/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP define arm_aapcs_vfpcc float @fmul_v2f32(<2 x float> %x, float %y) { ; CHECK-LABEL: fmul_v2f32: diff --git a/test/CodeGen/Thumb2/mve-vecreduce-mla.ll b/test/CodeGen/Thumb2/mve-vecreduce-mla.ll index dea70df6877..0716f585baf 100644 --- a/test/CodeGen/Thumb2/mve-vecreduce-mla.ll +++ b/test/CodeGen/Thumb2/mve-vecreduce-mla.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: add_v4i32_v4i32: diff --git a/test/CodeGen/Thumb2/mve-vector-spill.ll b/test/CodeGen/Thumb2/mve-vector-spill.ll index f7a0a04af79..3a33825a0b0 100644 --- a/test/CodeGen/Thumb2/mve-vector-spill.ll +++ b/test/CodeGen/Thumb2/mve-vector-spill.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -O0 -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -O0 -mattr=+mve %s -o - | FileCheck %s declare void @external_function() diff --git a/test/CodeGen/Thumb2/mve-vfma.ll b/test/CodeGen/Thumb2/mve-vfma.ll index 8ed8b81201e..1b071c709ce 100644 --- a/test/CodeGen/Thumb2/mve-vfma.ll +++ b/test/CodeGen/Thumb2/mve-vfma.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x float> @fma_v4f32(<4 x float> %dst, <4 x float> %s1, <4 x float> %s2) { ; CHECK-LABEL: fma_v4f32: diff --git a/test/CodeGen/Thumb2/mve-vhaddsub.ll b/test/CodeGen/Thumb2/mve-vhaddsub.ll index d70dff938ec..08e76ec185f 100644 --- a/test/CodeGen/Thumb2/mve-vhaddsub.ll +++ b/test/CodeGen/Thumb2/mve-vhaddsub.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @add_ashr_v16i8(<16 x i8> %src1, <16 x i8> %src2) { ; CHECK-LABEL: add_ashr_v16i8: diff --git a/test/CodeGen/Thumb2/mve-vld2-post.ll b/test/CodeGen/Thumb2/mve-vld2-post.ll index 11bf7b5900c..0a5f2105868 100644 --- a/test/CodeGen/Thumb2/mve-vld2-post.ll +++ b/test/CodeGen/Thumb2/mve-vld2-post.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/test/CodeGen/Thumb2/mve-vld2.ll b/test/CodeGen/Thumb2/mve-vld2.ll index 24e69c12a34..7c8c0bae6be 100644 --- a/test/CodeGen/Thumb2/mve-vld2.ll +++ b/test/CodeGen/Thumb2/mve-vld2.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/test/CodeGen/Thumb2/mve-vld3.ll b/test/CodeGen/Thumb2/mve-vld3.ll index 3b49d77ba6f..02e90a78dae 100644 --- a/test/CodeGen/Thumb2/mve-vld3.ll +++ b/test/CodeGen/Thumb2/mve-vld3.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/test/CodeGen/Thumb2/mve-vld4-post.ll b/test/CodeGen/Thumb2/mve-vld4-post.ll index 7a9d20c5c95..e8f33687132 100644 --- a/test/CodeGen/Thumb2/mve-vld4-post.ll +++ b/test/CodeGen/Thumb2/mve-vld4-post.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/test/CodeGen/Thumb2/mve-vld4.ll b/test/CodeGen/Thumb2/mve-vld4.ll index 9a132098694..233082a14a9 100644 --- a/test/CodeGen/Thumb2/mve-vld4.ll +++ b/test/CodeGen/Thumb2/mve-vld4.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/test/CodeGen/Thumb2/mve-vldst4.ll b/test/CodeGen/Thumb2/mve-vldst4.ll index a1b47029e4a..5c4d982d66a 100644 --- a/test/CodeGen/Thumb2/mve-vldst4.ll +++ b/test/CodeGen/Thumb2/mve-vldst4.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 { ; CHECK-LABEL: vldst4: diff --git a/test/CodeGen/Thumb2/mve-vmaxv.ll b/test/CodeGen/Thumb2/mve-vmaxv.ll index 4c705b75fd7..f96c2f422a3 100644 --- a/test/CodeGen/Thumb2/mve-vmaxv.ll +++ b/test/CodeGen/Thumb2/mve-vmaxv.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s declare i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8>) declare i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16>) diff --git a/test/CodeGen/Thumb2/mve-vmla.ll b/test/CodeGen/Thumb2/mve-vmla.ll index 5b0bdebfa88..9c5b405dbc3 100644 --- a/test/CodeGen/Thumb2/mve-vmla.ll +++ b/test/CodeGen/Thumb2/mve-vmla.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vmlau32(<4 x i32> %A, <4 x i32> %B, i32 %X) nounwind { ; CHECK-LABEL: vmlau32: diff --git a/test/CodeGen/Thumb2/mve-vmovimm.ll b/test/CodeGen/Thumb2/mve-vmovimm.ll index aad885b9b18..4dd2470d1b3 100644 --- a/test/CodeGen/Thumb2/mve-vmovimm.ll +++ b/test/CodeGen/Thumb2/mve-vmovimm.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKBE define arm_aapcs_vfpcc <16 x i8> @mov_int8_1() { diff --git a/test/CodeGen/Thumb2/mve-vmovn.ll b/test/CodeGen/Thumb2/mve-vmovn.ll index 0a48179a21d..a70491a05c1 100644 --- a/test/CodeGen/Thumb2/mve-vmovn.ll +++ b/test/CodeGen/Thumb2/mve-vmovn.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECKBE define arm_aapcs_vfpcc <8 x i16> @vmovn32_trunc1(<4 x i32> %src1, <4 x i32> %src2) { diff --git a/test/CodeGen/Thumb2/mve-vmovnstore.ll b/test/CodeGen/Thumb2/mve-vmovnstore.ll index 566e79780a4..b9856298def 100644 --- a/test/CodeGen/Thumb2/mve-vmovnstore.ll +++ b/test/CodeGen/Thumb2/mve-vmovnstore.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc void @vmovn32_trunc1(<4 x i32> %src1, <4 x i32> %src2, <8 x i16> *%dest) { ; CHECK-LABEL: vmovn32_trunc1: diff --git a/test/CodeGen/Thumb2/mve-vmull-loop.ll b/test/CodeGen/Thumb2/mve-vmull-loop.ll index 927a91233d5..ecb119888c8 100644 --- a/test/CodeGen/Thumb2/mve-vmull-loop.ll +++ b/test/CodeGen/Thumb2/mve-vmull-loop.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK define arm_aapcs_vfpcc void @test32(i32* noalias nocapture readonly %x, i32* noalias nocapture readonly %y, i32* nocapture %z, i32 %n) { ; CHECK-LABEL: test32: diff --git a/test/CodeGen/Thumb2/mve-vmull.ll b/test/CodeGen/Thumb2/mve-vmull.ll index 6d0b6622b8a..9d71df8dcca 100644 --- a/test/CodeGen/Thumb2/mve-vmull.ll +++ b/test/CodeGen/Thumb2/mve-vmull.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK define arm_aapcs_vfpcc <2 x i64> @sext_02(<4 x i32> %src1, <4 x i32> %src2) { ; CHECK-LABEL: sext_02: diff --git a/test/CodeGen/Thumb2/mve-vmulqr.ll b/test/CodeGen/Thumb2/mve-vmulqr.ll index 5c5c39c1554..b2eaf455ebe 100644 --- a/test/CodeGen/Thumb2/mve-vmulqr.ll +++ b/test/CodeGen/Thumb2/mve-vmulqr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vmulqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: vmulqr_v4i32: diff --git a/test/CodeGen/Thumb2/mve-vmvnimm.ll b/test/CodeGen/Thumb2/mve-vmvnimm.ll index 8f6ea13befc..a54d005444f 100644 --- a/test/CodeGen/Thumb2/mve-vmvnimm.ll +++ b/test/CodeGen/Thumb2/mve-vmvnimm.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <8 x i16> @mov_int16_511() { ; CHECK-LABEL: mov_int16_511: diff --git a/test/CodeGen/Thumb2/mve-vpsel.ll b/test/CodeGen/Thumb2/mve-vpsel.ll index 5da0aa518c0..fa897c5fe9d 100644 --- a/test/CodeGen/Thumb2/mve-vpsel.ll +++ b/test/CodeGen/Thumb2/mve-vpsel.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @vpsel_i8(<16 x i8> %mask, <16 x i8> %src1, <16 x i8> %src2) { ; CHECK-LABEL: vpsel_i8: diff --git a/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir b/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir index 1aa281841fd..f1495509df6 100644 --- a/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir +++ b/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_1_pred(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) local_unnamed_addr #0 { entry: diff --git a/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir b/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir index a8b0edefe39..506b8d2687c 100644 --- a/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir +++ b/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_2_preds(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) local_unnamed_addr #0 { entry: diff --git a/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir b/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir index 4ac7f1152d6..391b74ee0da 100644 --- a/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir +++ b/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_ctrl_flow(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir b/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir index 8747eda183d..ee26f56b605 100644 --- a/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir +++ b/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_non_consecutive_ins(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir b/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir index a6414fbffda..594df596959 100644 --- a/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir +++ b/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir b/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir index 7401d771d1b..a60c217404b 100644 --- a/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir +++ b/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_3_blocks_kill_vpr(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir b/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir index 6f73c3535d4..858bb6a1562 100644 --- a/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir +++ b/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_1_ins(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir b/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir index b87edd64e92..eb47791e4f8 100644 --- a/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir +++ b/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_2_ins(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir b/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir index 9fb071b0e18..8504ad0814c 100644 --- a/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir +++ b/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_4_ins(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/test/CodeGen/Thumb2/mve-vpt-block-elses.mir b/test/CodeGen/Thumb2/mve-vpt-block-elses.mir index 93bf2e6f451..94cad747734 100644 --- a/test/CodeGen/Thumb2/mve-vpt-block-elses.mir +++ b/test/CodeGen/Thumb2/mve-vpt-block-elses.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_else(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir b/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir index ffc072bccbb..91643e5ccfa 100644 --- a/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir +++ b/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/test/CodeGen/Thumb2/mve-vpt-blocks.ll b/test/CodeGen/Thumb2/mve-vpt-blocks.ll index 94374308e7d..1c26ddd27f5 100644 --- a/test/CodeGen/Thumb2/mve-vpt-blocks.ll +++ b/test/CodeGen/Thumb2/mve-vpt-blocks.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi --verify-machineinstrs -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi --verify-machineinstrs -mattr=+mve.fp %s -o - | FileCheck %s declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) diff --git a/test/CodeGen/Thumb2/mve-vpt-optimisations.mir b/test/CodeGen/Thumb2/mve-vpt-optimisations.mir index 49677433543..7e14d074604 100644 --- a/test/CodeGen/Thumb2/mve-vpt-optimisations.mir +++ b/test/CodeGen/Thumb2/mve-vpt-optimisations.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" ; Functions are intentionally left blank - see the MIR sequences below. diff --git a/test/CodeGen/Thumb2/mve-vpt-preuse.mir b/test/CodeGen/Thumb2/mve-vpt-preuse.mir index e49a870bced..fe6f4a3f595 100644 --- a/test/CodeGen/Thumb2/mve-vpt-preuse.mir +++ b/test/CodeGen/Thumb2/mve-vpt-preuse.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define arm_aapcs_vfpcc <4 x float> @vpt_preuse(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) #0 { entry: diff --git a/test/CodeGen/Thumb2/mve-vqmovn.ll b/test/CodeGen/Thumb2/mve-vqmovn.ll index f8d70fcd449..0478ae19933 100644 --- a/test/CodeGen/Thumb2/mve-vqmovn.ll +++ b/test/CodeGen/Thumb2/mve-vqmovn.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vqmovni32_smaxmin(<4 x i32> %s0) { ; CHECK-LABEL: vqmovni32_smaxmin: diff --git a/test/CodeGen/Thumb2/mve-vst2-post.ll b/test/CodeGen/Thumb2/mve-vst2-post.ll index e6bbf4d7e77..ebaeae88af7 100644 --- a/test/CodeGen/Thumb2/mve-vst2-post.ll +++ b/test/CodeGen/Thumb2/mve-vst2-post.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/test/CodeGen/Thumb2/mve-vst2.ll b/test/CodeGen/Thumb2/mve-vst2.ll index 5eea2531ee0..9b68f7d4c07 100644 --- a/test/CodeGen/Thumb2/mve-vst2.ll +++ b/test/CodeGen/Thumb2/mve-vst2.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/test/CodeGen/Thumb2/mve-vst3.ll b/test/CodeGen/Thumb2/mve-vst3.ll index 614db5ff829..167076e5c11 100644 --- a/test/CodeGen/Thumb2/mve-vst3.ll +++ b/test/CodeGen/Thumb2/mve-vst3.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/test/CodeGen/Thumb2/mve-vst4-post.ll b/test/CodeGen/Thumb2/mve-vst4-post.ll index d8f674ac9c1..4c939fc09e5 100644 --- a/test/CodeGen/Thumb2/mve-vst4-post.ll +++ b/test/CodeGen/Thumb2/mve-vst4-post.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/test/CodeGen/Thumb2/mve-vst4.ll b/test/CodeGen/Thumb2/mve-vst4.ll index 9aeda408720..bc541556642 100644 --- a/test/CodeGen/Thumb2/mve-vst4.ll +++ b/test/CodeGen/Thumb2/mve-vst4.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/test/CodeGen/Thumb2/mve-vsubqr.ll b/test/CodeGen/Thumb2/mve-vsubqr.ll index ec2f7c11b52..946b2ed4978 100644 --- a/test/CodeGen/Thumb2/mve-vsubqr.ll +++ b/test/CodeGen/Thumb2/mve-vsubqr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vsubqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: vsubqr_v4i32: diff --git a/test/CodeGen/Thumb2/mve-widen-narrow.ll b/test/CodeGen/Thumb2/mve-widen-narrow.ll index 4c3b4d3e1b3..033a0712504 100644 --- a/test/CodeGen/Thumb2/mve-widen-narrow.ll +++ b/test/CodeGen/Thumb2/mve-widen-narrow.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define void @foo_int8_int32(<4 x i8>* %dest, <4 x i32>* readonly %src, i32 %n) { diff --git a/test/CodeGen/Thumb2/postinc-distribute.mir b/test/CodeGen/Thumb2/postinc-distribute.mir index 77b401fba1f..af39cced110 100644 --- a/test/CodeGen/Thumb2/postinc-distribute.mir +++ b/test/CodeGen/Thumb2/postinc-distribute.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s --- | define i32* @t2LDRi12(i32* %x, i32 %y) { unreachable } diff --git a/test/CodeGen/Thumb2/vqabs.ll b/test/CodeGen/Thumb2/vqabs.ll index 7a366ea5ed0..3525413f9c4 100644 --- a/test/CodeGen/Thumb2/vqabs.ll +++ b/test/CodeGen/Thumb2/vqabs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @vqabs_test16(<16 x i8> %A) nounwind { ; CHECK-LABEL: vqabs_test16: diff --git a/test/CodeGen/Thumb2/vqneg.ll b/test/CodeGen/Thumb2/vqneg.ll index b92a7ab270f..6c702f3839b 100644 --- a/test/CodeGen/Thumb2/vqneg.ll +++ b/test/CodeGen/Thumb2/vqneg.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @vqneg_test16(<16 x i8> %A) nounwind { ; CHECK-LABEL: vqneg_test16: diff --git a/test/MC/ARM/vscclrm-asm.s b/test/MC/ARM/vscclrm-asm.s index 3f679c7fdd0..0989b38b07c 100644 --- a/test/MC/ARM/vscclrm-asm.s +++ b/test/MC/ARM/vscclrm-asm.s @@ -4,7 +4,7 @@ // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+8msecext -show-encoding < %s 2>%t \ // RUN: | FileCheck --check-prefix=CHECK %s // RUN: FileCheck --check-prefix=ERROR < %t %s -// RUN: not llvm-mc -triple=thumbv8.1m.main-arm-none-eabi -mattr=-8msecext < %s 2>%t +// RUN: not llvm-mc -triple=thumbv8.1m.main-none-none-eabi -mattr=-8msecext < %s 2>%t // RUN: FileCheck --check-prefix=NOSEC < %t %s // CHECK: vscclrm {s0, s1, s2, s3, vpr} @ encoding: [0x9f,0xec,0x04,0x0a] diff --git a/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll b/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll index cb0737ffaeb..54988e69c29 100644 --- a/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll +++ b/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp < %s -codegenprepare -S | FileCheck -check-prefix=CHECK %s +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp < %s -codegenprepare -S | FileCheck -check-prefix=CHECK %s define void @sink_add_mul(i32* %s1, i32 %x, i32* %d, i32 %n) { ; CHECK-LABEL: @sink_add_mul( diff --git a/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll b/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll index c0da3eb5666..470a9f20179 100644 --- a/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll +++ b/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp < %s -codegenprepare -S | FileCheck -check-prefix=CHECK %s +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp < %s -codegenprepare -S | FileCheck -check-prefix=CHECK %s ; Sink the shufflevector/insertelement pair, followed by the trunc. The sunk instruction end up dead. define signext i8 @dead(i16* noalias nocapture readonly %s1, i16 zeroext %x, i8* noalias nocapture %d, i32 %n) { diff --git a/test/Transforms/HardwareLoops/ARM/calls-codegen.ll b/test/Transforms/HardwareLoops/ARM/calls-codegen.ll index 2771235d576..72b5bb0c7be 100644 --- a/test/Transforms/HardwareLoops/ARM/calls-codegen.ll +++ b/test/Transforms/HardwareLoops/ARM/calls-codegen.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+lob,+mve.fp -disable-arm-loloops=true %s -o - | FileCheck %s --check-prefix=DISABLED -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+lob,+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+lob,+mve.fp -disable-arm-loloops=true %s -o - | FileCheck %s --check-prefix=DISABLED +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+lob,+mve.fp %s -o - | FileCheck %s ; DISABLED-NOT: dls lr, diff --git a/test/Transforms/HardwareLoops/ARM/calls.ll b/test/Transforms/HardwareLoops/ARM/calls.ll index 43c6d06a108..feb6b6574a1 100644 --- a/test/Transforms/HardwareLoops/ARM/calls.ll +++ b/test/Transforms/HardwareLoops/ARM/calls.ll @@ -1,9 +1,9 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MAIN -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+fullfp16 -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+fp-armv8,+fullfp16 -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP64 -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops -disable-arm-loloops=true %s -S -o - | FileCheck %s --check-prefix=DISABLED +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MAIN +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fullfp16 -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fp-armv8,+fullfp16 -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP64 +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops -disable-arm-loloops=true %s -S -o - | FileCheck %s --check-prefix=DISABLED ; DISABLED-NOT: call i32 @llvm.loop.decrement diff --git a/test/Transforms/HardwareLoops/ARM/counter.ll b/test/Transforms/HardwareLoops/ARM/counter.ll index edb63546428..fd216d9f356 100644 --- a/test/Transforms/HardwareLoops/ARM/counter.ll +++ b/test/Transforms/HardwareLoops/ARM/counter.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops %s -o - | FileCheck %s +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops %s -o - | FileCheck %s @g = common local_unnamed_addr global i32* null, align 4 diff --git a/test/Transforms/HardwareLoops/ARM/do-rem.ll b/test/Transforms/HardwareLoops/ARM/do-rem.ll index c3e0d88d8df..ed89a5ad475 100644 --- a/test/Transforms/HardwareLoops/ARM/do-rem.ll +++ b/test/Transforms/HardwareLoops/ARM/do-rem.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops %s -S -o - | FileCheck %s +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops %s -S -o - | FileCheck %s @g = common local_unnamed_addr global i32* null, align 4 diff --git a/test/Transforms/HardwareLoops/ARM/fp-emulation.ll b/test/Transforms/HardwareLoops/ARM/fp-emulation.ll index 4bf76b6cdc8..66a97b2321e 100644 --- a/test/Transforms/HardwareLoops/ARM/fp-emulation.ll +++ b/test/Transforms/HardwareLoops/ARM/fp-emulation.ll @@ -1,5 +1,5 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+fp-armv8 -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+soft-float -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SOFT +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fp-armv8 -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+soft-float -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SOFT ; CHECK-LABEL: test_fptosi ; CHECK-SOFT-NOT: call void @llvm.set.loop.iterations diff --git a/test/Transforms/HardwareLoops/ARM/simple-do.ll b/test/Transforms/HardwareLoops/ARM/simple-do.ll index 8d5cdc1a3fe..780098049b2 100644 --- a/test/Transforms/HardwareLoops/ARM/simple-do.ll +++ b/test/Transforms/HardwareLoops/ARM/simple-do.ll @@ -1,6 +1,6 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops %s -S -o - | FileCheck %s -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops -disable-arm-loloops=true %s -S -o - | FileCheck %s --check-prefix=DISABLED -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -o - | FileCheck %s --check-prefix=CHECK-LLC +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops %s -S -o - | FileCheck %s +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops -disable-arm-loloops=true %s -S -o - | FileCheck %s --check-prefix=DISABLED +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi %s -o - | FileCheck %s --check-prefix=CHECK-LLC ; DISABLED-NOT: llvm.{{.*}}.loop.iterations ; DISABLED-NOT: llvm.loop.decrement diff --git a/test/Transforms/HardwareLoops/ARM/structure.ll b/test/Transforms/HardwareLoops/ARM/structure.ll index fbc09a175f8..1a668864003 100644 --- a/test/Transforms/HardwareLoops/ARM/structure.ll +++ b/test/Transforms/HardwareLoops/ARM/structure.ll @@ -1,10 +1,10 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops %s -S -o - | \ +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops %s -S -o - | \ ; RUN: FileCheck %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -o - | \ +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi %s -o - | \ ; RUN: FileCheck %s --check-prefix=CHECK-LLC ; RUN: opt -mtriple=thumbv8.1m.main -loop-unroll -unroll-remainder=false -S < %s | \ ; RUN: llc -mtriple=thumbv8.1m.main | FileCheck %s --check-prefix=CHECK-UNROLL -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops \ +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops \ ; RUN: -pass-remarks-analysis=hardware-loops %s -S -o - 2>&1 | \ ; RUN: FileCheck %s --check-prefix=CHECK-REMARKS diff --git a/test/Transforms/LoopVectorize/ARM/mve-reduce.ll b/test/Transforms/LoopVectorize/ARM/mve-reduce.ll index e1a4c9ea6c5..807de5614b8 100644 --- a/test/Transforms/LoopVectorize/ARM/mve-reduce.ll +++ b/test/Transforms/LoopVectorize/ARM/mve-reduce.ll @@ -1,7 +1,7 @@ ; RUN: opt -loop-vectorize < %s -S -o - | FileCheck %s target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" -target triple = "thumbv8.1m.main-arm-none-eabi" +target triple = "thumbv8.1m.main-none-none-eabi" ; CHECK-LABEL: check4 ; CHECK: call i32 @llvm.experimental.vector.reduce.add.v4i32 diff --git a/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll b/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll index 7195e61c280..15c8483685b 100644 --- a/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll +++ b/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll @@ -3,7 +3,7 @@ ; REQUIRES: asserts target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" -target triple = "thumbv8.1m.main-arm-none-eabi" +target triple = "thumbv8.1m.main-none-none-eabi" ; CHECK-LABEL: test ; CHECK-COST: LV: Found an estimated cost of 0 for VF 1 For instruction: %and515 = shl i32 %l41, 3 diff --git a/test/Transforms/LoopVectorize/ARM/mve-vldn.ll b/test/Transforms/LoopVectorize/ARM/mve-vldn.ll index 353e725580a..49d13f7fc01 100644 --- a/test/Transforms/LoopVectorize/ARM/mve-vldn.ll +++ b/test/Transforms/LoopVectorize/ARM/mve-vldn.ll @@ -4,7 +4,7 @@ ; RUN: opt -loop-vectorize -mve-max-interleave-factor=4 < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-2,CHECK-4 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" -target triple = "thumbv8.1m.main-arm-none-eabi" +target triple = "thumbv8.1m.main-none-none-eabi" ; CHECK-LABEL: vld2 ; CHECK-2: vector.body diff --git a/unittests/Target/ARM/MachineInstrTest.cpp b/unittests/Target/ARM/MachineInstrTest.cpp index 6cf8493666b..51c9d739f91 100644 --- a/unittests/Target/ARM/MachineInstrTest.cpp +++ b/unittests/Target/ARM/MachineInstrTest.cpp @@ -74,7 +74,7 @@ TEST(MachineInstructionDoubleWidthResult, IsCorrect) { LLVMInitializeARMTarget(); LLVMInitializeARMTargetMC(); - auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi")); + auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi")); std::string Error; const Target *T = TargetRegistry::lookupTarget(TT, Error); if (!T) { @@ -231,7 +231,7 @@ TEST(MachineInstructionHorizontalReduction, IsCorrect) { LLVMInitializeARMTarget(); LLVMInitializeARMTargetMC(); - auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi")); + auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi")); std::string Error; const Target *T = TargetRegistry::lookupTarget(TT, Error); if (!T) { @@ -331,7 +331,7 @@ TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) { LLVMInitializeARMTarget(); LLVMInitializeARMTargetMC(); - auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi")); + auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi")); std::string Error; const Target *T = TargetRegistry::lookupTarget(TT, Error); if (!T) { @@ -932,7 +932,7 @@ TEST(MachineInstrValidTailPredication, IsCorrect) { LLVMInitializeARMTarget(); LLVMInitializeARMTargetMC(); - auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi")); + auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi")); std::string Error; const Target *T = TargetRegistry::lookupTarget(TT, Error); if (!T) { @@ -986,7 +986,7 @@ TEST(MachineInstr, HasSideEffects) { LLVMInitializeARMTarget(); LLVMInitializeARMTargetMC(); - auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi")); + auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi")); std::string Error; const Target *T = TargetRegistry::lookupTarget(TT, Error); if (!T) {