mirror of
https://github.com/RPCS3/llvm-mirror.git
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[MiSched|TableGen] : Tidy up and modernise. NFC.
Replacing with range-based loop and substituting 'using'. Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D37748 llvm-svn: 313140
This commit is contained in:
Javed Absar
parent
599ad8ebac
commit
6e732d4dbb
@ -162,8 +162,8 @@ void CodeGenSchedModels::collectProcModels() {
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// For each processor, find a unique machine model.
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DEBUG(dbgs() << "+++ PROCESSOR MODELs (addProcModel) +++\n");
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for (unsigned i = 0, N = ProcRecords.size(); i < N; ++i)
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addProcModel(ProcRecords[i]);
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for (Record *ProcRecord : ProcRecords)
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addProcModel(ProcRecord);
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}
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/// Get a unique processor model based on the defined MachineModel and
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@ -194,20 +194,20 @@ static void scanSchedRW(Record *RWDef, RecVec &RWDefs,
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if (!RWSet.insert(RWDef).second)
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return;
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RWDefs.push_back(RWDef);
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// Reads don't current have sequence records, but it can be added later.
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// Reads don't currently have sequence records, but it can be added later.
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if (RWDef->isSubClassOf("WriteSequence")) {
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RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
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for (RecIter I = Seq.begin(), E = Seq.end(); I != E; ++I)
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scanSchedRW(*I, RWDefs, RWSet);
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for (Record *WSRec : Seq)
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scanSchedRW(WSRec, RWDefs, RWSet);
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}
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else if (RWDef->isSubClassOf("SchedVariant")) {
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// Visit each variant (guarded by a different predicate).
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RecVec Vars = RWDef->getValueAsListOfDefs("Variants");
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for (RecIter VI = Vars.begin(), VE = Vars.end(); VI != VE; ++VI) {
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for (Record *Variant : Vars) {
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// Visit each RW in the sequence selected by the current variant.
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RecVec Selected = (*VI)->getValueAsListOfDefs("Selected");
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for (RecIter I = Selected.begin(), E = Selected.end(); I != E; ++I)
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scanSchedRW(*I, RWDefs, RWSet);
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RecVec Selected = Variant->getValueAsListOfDefs("Selected");
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for (Record *SelDef : Selected)
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scanSchedRW(SelDef, RWDefs, RWSet);
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}
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}
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}
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@ -228,42 +228,40 @@ void CodeGenSchedModels::collectSchedRW() {
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if (SchedDef->isValueUnset("SchedRW"))
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continue;
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RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
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for (RecIter RWI = RWs.begin(), RWE = RWs.end(); RWI != RWE; ++RWI) {
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if ((*RWI)->isSubClassOf("SchedWrite"))
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scanSchedRW(*RWI, SWDefs, RWSet);
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for (Record *RW : RWs) {
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if (RW->isSubClassOf("SchedWrite"))
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scanSchedRW(RW, SWDefs, RWSet);
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else {
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assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
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scanSchedRW(*RWI, SRDefs, RWSet);
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assert(RW->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
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scanSchedRW(RW, SRDefs, RWSet);
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}
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}
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}
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// Find all ReadWrites referenced by InstRW.
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RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
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for (RecIter OI = InstRWDefs.begin(), OE = InstRWDefs.end(); OI != OE; ++OI) {
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for (Record *InstRWDef : InstRWDefs) {
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// For all OperandReadWrites.
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RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites");
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for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end();
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RWI != RWE; ++RWI) {
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if ((*RWI)->isSubClassOf("SchedWrite"))
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scanSchedRW(*RWI, SWDefs, RWSet);
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RecVec RWDefs = InstRWDef->getValueAsListOfDefs("OperandReadWrites");
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for (Record *RWDef : RWDefs) {
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if (RWDef->isSubClassOf("SchedWrite"))
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scanSchedRW(RWDef, SWDefs, RWSet);
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else {
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assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
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scanSchedRW(*RWI, SRDefs, RWSet);
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assert(RWDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
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scanSchedRW(RWDef, SRDefs, RWSet);
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}
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}
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}
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// Find all ReadWrites referenced by ItinRW.
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RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");
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for (RecIter II = ItinRWDefs.begin(), IE = ItinRWDefs.end(); II != IE; ++II) {
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for (Record *ItinRWDef : ItinRWDefs) {
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// For all OperandReadWrites.
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RecVec RWDefs = (*II)->getValueAsListOfDefs("OperandReadWrites");
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for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end();
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RWI != RWE; ++RWI) {
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if ((*RWI)->isSubClassOf("SchedWrite"))
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scanSchedRW(*RWI, SWDefs, RWSet);
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RecVec RWDefs = ItinRWDef->getValueAsListOfDefs("OperandReadWrites");
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for (Record *RWDef : RWDefs) {
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if (RWDef->isSubClassOf("SchedWrite"))
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scanSchedRW(RWDef, SWDefs, RWSet);
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else {
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assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
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scanSchedRW(*RWI, SRDefs, RWSet);
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assert(RWDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
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scanSchedRW(RWDef, SRDefs, RWSet);
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}
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}
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}
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@ -271,50 +269,49 @@ void CodeGenSchedModels::collectSchedRW() {
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// for the loop below that initializes Alias vectors.
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RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias");
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std::sort(AliasDefs.begin(), AliasDefs.end(), LessRecord());
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for (RecIter AI = AliasDefs.begin(), AE = AliasDefs.end(); AI != AE; ++AI) {
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Record *MatchDef = (*AI)->getValueAsDef("MatchRW");
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Record *AliasDef = (*AI)->getValueAsDef("AliasRW");
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for (Record *ADef : AliasDefs) {
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Record *MatchDef = ADef->getValueAsDef("MatchRW");
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Record *AliasDef = ADef->getValueAsDef("AliasRW");
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if (MatchDef->isSubClassOf("SchedWrite")) {
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if (!AliasDef->isSubClassOf("SchedWrite"))
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PrintFatalError((*AI)->getLoc(), "SchedWrite Alias must be SchedWrite");
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PrintFatalError(ADef->getLoc(), "SchedWrite Alias must be SchedWrite");
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scanSchedRW(AliasDef, SWDefs, RWSet);
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}
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else {
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assert(MatchDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
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if (!AliasDef->isSubClassOf("SchedRead"))
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PrintFatalError((*AI)->getLoc(), "SchedRead Alias must be SchedRead");
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PrintFatalError(ADef->getLoc(), "SchedRead Alias must be SchedRead");
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scanSchedRW(AliasDef, SRDefs, RWSet);
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}
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}
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// Sort and add the SchedReadWrites directly referenced by instructions or
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// itinerary resources. Index reads and writes in separate domains.
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std::sort(SWDefs.begin(), SWDefs.end(), LessRecord());
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for (RecIter SWI = SWDefs.begin(), SWE = SWDefs.end(); SWI != SWE; ++SWI) {
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assert(!getSchedRWIdx(*SWI, /*IsRead=*/false) && "duplicate SchedWrite");
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SchedWrites.emplace_back(SchedWrites.size(), *SWI);
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for (Record *SWDef : SWDefs) {
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assert(!getSchedRWIdx(SWDef, /*IsRead=*/false) && "duplicate SchedWrite");
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SchedWrites.emplace_back(SchedWrites.size(), SWDef);
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}
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std::sort(SRDefs.begin(), SRDefs.end(), LessRecord());
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for (RecIter SRI = SRDefs.begin(), SRE = SRDefs.end(); SRI != SRE; ++SRI) {
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assert(!getSchedRWIdx(*SRI, /*IsRead-*/true) && "duplicate SchedWrite");
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SchedReads.emplace_back(SchedReads.size(), *SRI);
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for (Record *SRDef : SRDefs) {
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assert(!getSchedRWIdx(SRDef, /*IsRead-*/true) && "duplicate SchedWrite");
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SchedReads.emplace_back(SchedReads.size(), SRDef);
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}
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// Initialize WriteSequence vectors.
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for (std::vector<CodeGenSchedRW>::iterator WI = SchedWrites.begin(),
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WE = SchedWrites.end(); WI != WE; ++WI) {
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if (!WI->IsSequence)
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for (CodeGenSchedRW &CGRW : SchedWrites) {
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if (!CGRW.IsSequence)
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continue;
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findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence,
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findRWs(CGRW.TheDef->getValueAsListOfDefs("Writes"), CGRW.Sequence,
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/*IsRead=*/false);
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}
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// Initialize Aliases vectors.
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for (RecIter AI = AliasDefs.begin(), AE = AliasDefs.end(); AI != AE; ++AI) {
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Record *AliasDef = (*AI)->getValueAsDef("AliasRW");
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for (Record *ADef : AliasDefs) {
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Record *AliasDef = ADef->getValueAsDef("AliasRW");
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getSchedRW(AliasDef).IsAlias = true;
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Record *MatchDef = (*AI)->getValueAsDef("MatchRW");
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Record *MatchDef = ADef->getValueAsDef("MatchRW");
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CodeGenSchedRW &RW = getSchedRW(MatchDef);
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if (RW.IsAlias)
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PrintFatalError((*AI)->getLoc(), "Cannot Alias an Alias");
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RW.Aliases.push_back(*AI);
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PrintFatalError(ADef->getLoc(), "Cannot Alias an Alias");
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RW.Aliases.push_back(ADef);
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}
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DEBUG(
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dbgs() << "\n+++ SCHED READS and WRITES (collectSchedRW) +++\n";
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@ -329,12 +326,11 @@ void CodeGenSchedModels::collectSchedRW() {
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dbgs() << '\n';
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}
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RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite");
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for (RecIter RI = RWDefs.begin(), RE = RWDefs.end();
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RI != RE; ++RI) {
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if (!getSchedRWIdx(*RI, (*RI)->isSubClassOf("SchedRead"))) {
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const std::string &Name = (*RI)->getName();
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for (Record *RWDef : RWDefs) {
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if (!getSchedRWIdx(RWDef, RWDef->isSubClassOf("SchedRead"))) {
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const std::string &Name = RWDef->getName();
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if (Name != "NoWrite" && Name != "ReadDefault")
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dbgs() << "Unused SchedReadWrite " << (*RI)->getName() << '\n';
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dbgs() << "Unused SchedReadWrite " << RWDef->getName() << '\n';
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}
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});
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}
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@ -364,8 +360,8 @@ unsigned CodeGenSchedModels::getSchedRWIdx(Record *Def, bool IsRead,
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}
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bool CodeGenSchedModels::hasReadOfWrite(Record *WriteDef) const {
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for (unsigned i = 0, e = SchedReads.size(); i < e; ++i) {
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Record *ReadDef = SchedReads[i].TheDef;
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for (const CodeGenSchedRW &Read : SchedReads) {
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Record *ReadDef = Read.TheDef;
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if (!ReadDef || !ReadDef->isSubClassOf("ProcReadAdvance"))
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continue;
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@ -381,12 +377,12 @@ namespace llvm {
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void splitSchedReadWrites(const RecVec &RWDefs,
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RecVec &WriteDefs, RecVec &ReadDefs) {
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for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end(); RWI != RWE; ++RWI) {
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if ((*RWI)->isSubClassOf("SchedWrite"))
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WriteDefs.push_back(*RWI);
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for (Record *RWDef : RWDefs) {
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if (RWDef->isSubClassOf("SchedWrite"))
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WriteDefs.push_back(RWDef);
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else {
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assert((*RWI)->isSubClassOf("SchedRead") && "unknown SchedReadWrite");
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ReadDefs.push_back(*RWI);
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assert(RWDef->isSubClassOf("SchedRead") && "unknown SchedReadWrite");
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ReadDefs.push_back(RWDef);
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}
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}
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}
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@ -406,8 +402,8 @@ void CodeGenSchedModels::findRWs(const RecVec &RWDefs,
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// Call getSchedRWIdx for all elements in a sequence of SchedRW defs.
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void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs,
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bool IsRead) const {
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for (RecIter RI = RWDefs.begin(), RE = RWDefs.end(); RI != RE; ++RI) {
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unsigned Idx = getSchedRWIdx(*RI, IsRead);
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for (Record *RWDef : RWDefs) {
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unsigned Idx = getSchedRWIdx(RWDef, IsRead);
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assert(Idx && "failed to collect SchedReadWrite");
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RWs.push_back(Idx);
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}
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@ -423,9 +419,8 @@ void CodeGenSchedModels::expandRWSequence(unsigned RWIdx, IdxVec &RWSeq,
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int Repeat =
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SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1;
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for (int i = 0; i < Repeat; ++i) {
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for (IdxIter I = SchedRW.Sequence.begin(), E = SchedRW.Sequence.end();
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I != E; ++I) {
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expandRWSequence(*I, RWSeq, IsRead);
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for (unsigned I : SchedRW.Sequence) {
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expandRWSequence(I, RWSeq, IsRead);
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}
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}
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}
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@ -464,9 +459,8 @@ void CodeGenSchedModels::expandRWSeqForProc(
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int Repeat =
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SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1;
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for (int i = 0; i < Repeat; ++i) {
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for (IdxIter I = SchedWrite.Sequence.begin(), E = SchedWrite.Sequence.end();
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I != E; ++I) {
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expandRWSeqForProc(*I, RWSeq, IsRead, ProcModel);
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for (unsigned I : SchedWrite.Sequence) {
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expandRWSeqForProc(I, RWSeq, IsRead, ProcModel);
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}
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}
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}
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@ -535,8 +529,8 @@ void CodeGenSchedModels::collectSchedClasses() {
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RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
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std::sort(InstRWDefs.begin(), InstRWDefs.end(), LessRecord());
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DEBUG(dbgs() << "\n+++ SCHED CLASSES (createInstRWClass) +++\n");
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for (RecIter OI = InstRWDefs.begin(), OE = InstRWDefs.end(); OI != OE; ++OI)
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createInstRWClass(*OI);
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for (Record *RWDef : InstRWDefs)
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createInstRWClass(RWDef);
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NumInstrSchedClasses = SchedClasses.size();
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@ -575,20 +569,19 @@ void CodeGenSchedModels::collectSchedClasses() {
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dbgs() << '\n';
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}
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const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;
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for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end();
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RWI != RWE; ++RWI) {
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for (Record *RWDef : RWDefs) {
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const CodeGenProcModel &ProcModel =
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getProcModel((*RWI)->getValueAsDef("SchedModel"));
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getProcModel(RWDef->getValueAsDef("SchedModel"));
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ProcIndices.push_back(ProcModel.Index);
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dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName;
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IdxVec Writes;
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IdxVec Reads;
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findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"),
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findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
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Writes, Reads);
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for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI)
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dbgs() << " " << SchedWrites[*WI].Name;
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for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI)
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dbgs() << " " << SchedReads[*RI].Name;
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for (unsigned WIdx : Writes)
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dbgs() << " " << SchedWrites[WIdx].Name;
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for (unsigned RIdx : Reads)
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dbgs() << " " << SchedReads[RIdx].Name;
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dbgs() << '\n';
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}
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// If ProcIndices contains zero, the class applies to all processors.
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@ -729,9 +722,8 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
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if (!RWDefs.empty()) {
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const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);
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unsigned OrigNumInstrs = 0;
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for (RecIter I = OrigInstDefs->begin(), E = OrigInstDefs->end();
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I != E; ++I) {
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if (InstrClassMap[*I] == OldSCIdx)
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for (Record *OIDef : make_range(OrigInstDefs->begin(), OrigInstDefs->end())) {
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if (InstrClassMap[OIDef] == OldSCIdx)
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++OrigNumInstrs;
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}
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if (OrigNumInstrs == InstDefs.size()) {
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@ -785,9 +777,8 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
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// True if collectProcItins found anything.
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bool CodeGenSchedModels::hasItineraries() const {
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for (CodeGenSchedModels::ProcIter PI = procModelBegin(), PE = procModelEnd();
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PI != PE; ++PI) {
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if (PI->hasItineraries())
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for (const CodeGenProcModel &PM : make_range(procModelBegin(),procModelEnd())) {
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if (PM.hasItineraries())
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return true;
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}
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return false;
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@ -1695,30 +1686,26 @@ Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind,
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assert(!ProcResourceDefs.empty());
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assert(!ProcResGroups.empty());
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for (RecIter RI = ProcResourceDefs.begin(), RE = ProcResourceDefs.end();
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RI != RE; ++RI) {
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if ((*RI)->getValueAsDef("Kind") == ProcResKind
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&& (*RI)->getValueAsDef("SchedModel") == PM.ModelDef) {
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for (Record *ProcResDef : ProcResourceDefs) {
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if (ProcResDef->getValueAsDef("Kind") == ProcResKind
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&& ProcResDef->getValueAsDef("SchedModel") == PM.ModelDef) {
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if (ProcUnitDef) {
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PrintFatalError((*RI)->getLoc(),
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PrintFatalError(ProcResDef->getLoc(),
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"Multiple ProcessorResourceUnits associated with "
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+ ProcResKind->getName());
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}
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ProcUnitDef = *RI;
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ProcUnitDef = ProcResDef;
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}
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}
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for (RecIter RI = ProcResGroups.begin(), RE = ProcResGroups.end();
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RI != RE; ++RI) {
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if (*RI == ProcResKind
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&& (*RI)->getValueAsDef("SchedModel") == PM.ModelDef) {
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for (Record *ProcResGroup : ProcResGroups) {
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if (ProcResGroup == ProcResKind
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&& ProcResGroup->getValueAsDef("SchedModel") == PM.ModelDef) {
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if (ProcUnitDef) {
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PrintFatalError((*RI)->getLoc(),
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PrintFatalError((ProcResGroup)->getLoc(),
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"Multiple ProcessorResourceUnits associated with "
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+ ProcResKind->getName());
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}
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ProcUnitDef = *RI;
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ProcUnitDef = ProcResGroup;
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}
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}
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if (!ProcUnitDef) {
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@ -1832,9 +1819,8 @@ void CodeGenSchedClass::dump(const CodeGenSchedModels* SchedModels) const {
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dbgs() << "\n ProcIdx: "; dumpIdxVec(ProcIndices); dbgs() << '\n';
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if (!Transitions.empty()) {
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dbgs() << "\n Transitions for Proc ";
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for (std::vector<CodeGenSchedTransition>::const_iterator
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TI = Transitions.begin(), TE = Transitions.end(); TI != TE; ++TI) {
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dumpIdxVec(TI->ProcIndices);
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for (const CodeGenSchedTransition &Transition : Transitions) {
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dumpIdxVec(Transition.ProcIndices);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -27,11 +27,11 @@ class CodeGenTarget;
|
||||
class CodeGenSchedModels;
|
||||
class CodeGenInstruction;
|
||||
|
||||
typedef std::vector<Record*> RecVec;
|
||||
typedef std::vector<Record*>::const_iterator RecIter;
|
||||
using RecVec = std::vector<Record*>;
|
||||
using RecIter = std::vector<Record*>::const_iterator;
|
||||
|
||||
typedef std::vector<unsigned> IdxVec;
|
||||
typedef std::vector<unsigned>::const_iterator IdxIter;
|
||||
using IdxVec = std::vector<unsigned>;
|
||||
using IdxIter = std::vector<unsigned>::const_iterator;
|
||||
|
||||
void splitSchedReadWrites(const RecVec &RWDefs,
|
||||
RecVec &WriteDefs, RecVec &ReadDefs);
|
||||
@ -234,7 +234,7 @@ class CodeGenSchedModels {
|
||||
std::vector<CodeGenProcModel> ProcModels;
|
||||
|
||||
// Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
|
||||
typedef DenseMap<Record*, unsigned> ProcModelMapTy;
|
||||
using ProcModelMapTy = DenseMap<Record*, unsigned>;
|
||||
ProcModelMapTy ProcModelMap;
|
||||
|
||||
// Per-operand SchedReadWrite types.
|
||||
@ -252,15 +252,15 @@ class CodeGenSchedModels {
|
||||
|
||||
// Map each instruction to its unique SchedClass index considering the
|
||||
// combination of it's itinerary class, SchedRW list, and InstRW records.
|
||||
typedef DenseMap<Record*, unsigned> InstClassMapTy;
|
||||
using InstClassMapTy = DenseMap<Record*, unsigned>;
|
||||
InstClassMapTy InstrClassMap;
|
||||
|
||||
public:
|
||||
CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
|
||||
|
||||
// iterator access to the scheduling classes.
|
||||
typedef std::vector<CodeGenSchedClass>::iterator class_iterator;
|
||||
typedef std::vector<CodeGenSchedClass>::const_iterator const_class_iterator;
|
||||
using class_iterator = std::vector<CodeGenSchedClass>::iterator;
|
||||
using const_class_iterator = std::vector<CodeGenSchedClass>::const_iterator;
|
||||
class_iterator classes_begin() { return SchedClasses.begin(); }
|
||||
const_class_iterator classes_begin() const { return SchedClasses.begin(); }
|
||||
class_iterator classes_end() { return SchedClasses.end(); }
|
||||
@ -306,7 +306,7 @@ public:
|
||||
}
|
||||
|
||||
// Iterate over the unique processor models.
|
||||
typedef std::vector<CodeGenProcModel>::const_iterator ProcIter;
|
||||
using ProcIter = std::vector<CodeGenProcModel>::const_iterator;
|
||||
ProcIter procModelBegin() const { return ProcModels.begin(); }
|
||||
ProcIter procModelEnd() const { return ProcModels.end(); }
|
||||
ArrayRef<CodeGenProcModel> procModels() const { return ProcModels; }
|
||||
@ -360,7 +360,7 @@ public:
|
||||
// for NoItinerary.
|
||||
unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
|
||||
|
||||
typedef std::vector<CodeGenSchedClass>::const_iterator SchedClassIter;
|
||||
using SchedClassIter = std::vector<CodeGenSchedClass>::const_iterator;
|
||||
SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
|
||||
SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
|
||||
ArrayRef<CodeGenSchedClass> schedClasses() const { return SchedClasses; }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user