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Swift Calling Convention: swiftcc for ARM.
Differential Revision: http://reviews.llvm.org/D18769 llvm-svn: 265482
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Manman Ren
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commit
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@ -430,6 +430,7 @@ added in the future:
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"``swiftcc``" - This calling convention is used for Swift language.
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- On X86-64 RCX and R8 are available for additional integer returns, and
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XMM2 and XMM3 are available for additional FP/vector returns.
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- On iOS platforms, we use AAPCS-VFP calling convention.
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"``cc <n>``" - Numbered convention
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Any calling convention may be specified by number, allowing
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target-specific calling conventions to be used. Target specific
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@ -1859,6 +1859,7 @@ CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
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return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
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}
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case CallingConv::ARM_AAPCS_VFP:
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case CallingConv::Swift:
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if (!isVarArg)
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return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
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// Fall through to soft float variant, variadic functions don't
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@ -3007,6 +3008,7 @@ bool ARMFastISel::fastLowerArguments() {
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case CallingConv::ARM_AAPCS_VFP:
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case CallingConv::ARM_AAPCS:
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case CallingConv::ARM_APCS:
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case CallingConv::Swift:
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break;
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}
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@ -1388,6 +1388,7 @@ ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
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case CallingConv::PreserveMost:
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return CallingConv::PreserveMost;
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case CallingConv::ARM_AAPCS_VFP:
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case CallingConv::Swift:
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return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
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case CallingConv::C:
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if (!Subtarget->isAAPCS_ABI())
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68
test/CodeGen/ARM/swift-ios.ll
Normal file
68
test/CodeGen/ARM/swift-ios.ll
Normal file
@ -0,0 +1,68 @@
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; RUN: llc -mtriple=armv7-apple-ios < %s | FileCheck %s
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define swiftcc float @t1(float %a, float %b) {
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entry:
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; CHECK: t1
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; CHECK-NOT: vmov
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; CHECK: vadd.f32
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%add = fadd float %a, %b
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ret float %add
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}
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define swiftcc double @t2(double %a, double %b) {
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entry:
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; CHECK: t2
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; CHECK-NOT: vmov
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; CHECK: vadd.f64
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%add = fadd double %a, %b
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ret double %add
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}
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define swiftcc double @t9(double %d0, double %d1, double %d2, double %d3,
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double %d4, double %d5, double %d6, double %d7, float %a, float %b) {
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entry:
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; CHECK-LABEL: t9:
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; CHECK-NOT: vmov
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; CHECK: vldr
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%add = fadd float %a, %b
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%conv = fpext float %add to double
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ret double %conv
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}
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define swiftcc double @t10(double %d0, double %d1, double %d2, double %d3,
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double %d4, double %d5, double %a, float %b, double %c) {
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entry:
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; CHECK-LABEL: t10:
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; CHECK-NOT: vmov
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; CHECK: vldr
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%add = fadd double %a, %c
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ret double %add
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}
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define swiftcc float @t11(double %d0, double %d1, double %d2, double %d3,
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double %d4, double %d5, double %d6, float %a, double %b, float %c) {
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entry:
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; CHECK-LABEL: t11:
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; CHECK: vldr
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%add = fadd float %a, %c
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ret float %add
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}
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define swiftcc double @t12(double %a, double %b) {
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entry:
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; CHECK-LABEL: t12:
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; CHECK: vstr
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%add = fadd double %a, %b
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%sub = fsub double %a, %b
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%call = tail call swiftcc double @x(double 0.000000e+00, double 0.000000e+00,
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double 0.000000e+00, double 0.000000e+00, double 0.000000e+00,
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double 0.000000e+00, double %add, float 0.000000e+00,
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double %sub)
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ret double %call
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}
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declare swiftcc double @x(double, double, double, double, double, double,
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double, float, double)
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attributes #0 = { readnone }
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attributes #1 = { readonly }
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133
test/CodeGen/ARM/swift-return.ll
Normal file
133
test/CodeGen/ARM/swift-return.ll
Normal file
@ -0,0 +1,133 @@
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; RUN: llc -mtriple=armv7k-apple-ios8.0 -mcpu=cortex-a7 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=armv7k-apple-ios8.0 -mcpu=cortex-a7 -verify-machineinstrs < %s -O0 | FileCheck --check-prefix=CHECK-O0 %s
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; RUN: llc -mtriple=armv7-apple-ios -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=armv7-apple-ios -verify-machineinstrs < %s -O0 | FileCheck --check-prefix=CHECK-O0 %s
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; Test how llvm handles return type of {i16, i8}. The return value will be
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; passed in %r0 and %r1.
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; CHECK-LABEL: test:
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; CHECK: bl {{.*}}gen
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; CHECK: sxth {{.*}}, r0
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; CHECK: sxtab r0, {{.*}}, r1
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; CHECK-O0-LABEL: test:
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; CHECK-O0: bl {{.*}}gen
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; CHECK-O0: sxth r0, r0
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; CHECK-O0: sxtb r1, r1
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; CHECK-O0: add r0, r0, r1
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define i16 @test(i32 %key) {
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entry:
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%key.addr = alloca i32, align 4
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store i32 %key, i32* %key.addr, align 4
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%0 = load i32, i32* %key.addr, align 4
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%call = call swiftcc { i16, i8 } @gen(i32 %0)
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%v3 = extractvalue { i16, i8 } %call, 0
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%v1 = sext i16 %v3 to i32
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%v5 = extractvalue { i16, i8 } %call, 1
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%v2 = sext i8 %v5 to i32
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%add = add nsw i32 %v1, %v2
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%conv = trunc i32 %add to i16
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ret i16 %conv
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}
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declare swiftcc { i16, i8 } @gen(i32)
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; We can't pass every return value in register, instead, pass everything in
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; memroy.
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; The caller provides space for the return value and passes the address in %r0.
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; The first input argument will be in %r1.
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; CHECK-LABEL: test2:
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; CHECK: mov r1, r0
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; CHECK: mov r0, sp
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; CHECK: bl {{.*}}gen2
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; CHECK-DAG: add
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; CHECK-DAG: ldr {{.*}}, [sp, #16]
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; CHECK-DAG: add
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; CHECK-DAG: add
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; CHECK-DAG: add
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; CHECK-O0-LABEL: test2:
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; CHECK-O0: str r0
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; CHECK-O0: mov r0, sp
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; CHECK-O0: bl {{.*}}gen2
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; CHECK-O0-DAG: ldr {{.*}}, [sp]
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; CHECK-O0-DAG: ldr {{.*}}, [sp, #4]
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; CHECK-O0-DAG: ldr {{.*}}, [sp, #8]
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; CHECK-O0-DAG: ldr {{.*}}, [sp, #12]
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; CHECK-O0-DAG: ldr {{.*}}, [sp, #16]
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; CHECK-O0-DAG: add
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; CHECK-O0-DAG: add
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; CHECK-O0-DAG: add
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; CHECK-O0-DAG: add
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define i32 @test2(i32 %key) #0 {
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entry:
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%key.addr = alloca i32, align 4
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store i32 %key, i32* %key.addr, align 4
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%0 = load i32, i32* %key.addr, align 4
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%call = call swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %0)
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%v3 = extractvalue { i32, i32, i32, i32, i32 } %call, 0
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%v5 = extractvalue { i32, i32, i32, i32, i32 } %call, 1
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%v6 = extractvalue { i32, i32, i32, i32, i32 } %call, 2
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%v7 = extractvalue { i32, i32, i32, i32, i32 } %call, 3
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%v8 = extractvalue { i32, i32, i32, i32, i32 } %call, 4
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%add = add nsw i32 %v3, %v5
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%add1 = add nsw i32 %add, %v6
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%add2 = add nsw i32 %add1, %v7
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%add3 = add nsw i32 %add2, %v8
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ret i32 %add3
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}
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; The address of the return value is passed in %r0.
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; CHECK-LABEL: gen2:
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; CHECK-DAG: str r1, [r0]
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; CHECK-DAG: str r1, [r0, #4]
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; CHECK-DAG: str r1, [r0, #8]
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; CHECK-DAG: str r1, [r0, #12]
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; CHECK-DAG: str r1, [r0, #16]
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; CHECK-O0-LABEL: gen2:
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; CHECK-O0-DAG: str r1, [r0]
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; CHECK-O0-DAG: str r1, [r0, #4]
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; CHECK-O0-DAG: str r1, [r0, #8]
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; CHECK-O0-DAG: str r1, [r0, #12]
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; CHECK-O0-DAG: str r1, [r0, #16]
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define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) {
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%Y = insertvalue { i32, i32, i32, i32, i32 } undef, i32 %key, 0
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%Z = insertvalue { i32, i32, i32, i32, i32 } %Y, i32 %key, 1
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%Z2 = insertvalue { i32, i32, i32, i32, i32 } %Z, i32 %key, 2
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%Z3 = insertvalue { i32, i32, i32, i32, i32 } %Z2, i32 %key, 3
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%Z4 = insertvalue { i32, i32, i32, i32, i32 } %Z3, i32 %key, 4
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ret { i32, i32, i32, i32, i32 } %Z4
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}
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; The return value {i32, i32, i32, i32} will be returned via registers %r0, %r1,
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; %r2, %r3.
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; CHECK-LABEL: test3:
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; CHECK: bl {{.*}}gen3
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; CHECK: add r0, r0, r1
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; CHECK: add r0, r0, r2
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; CHECK: add r0, r0, r3
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; CHECK-O0-LABEL: test3:
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; CHECK-O0: bl {{.*}}gen3
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; CHECK-O0: add r0, r0, r1
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; CHECK-O0: add r0, r0, r2
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; CHECK-O0: add r0, r0, r3
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define i32 @test3(i32 %key) #0 {
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entry:
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%key.addr = alloca i32, align 4
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store i32 %key, i32* %key.addr, align 4
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%0 = load i32, i32* %key.addr, align 4
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%call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0)
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%v3 = extractvalue { i32, i32, i32, i32 } %call, 0
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%v5 = extractvalue { i32, i32, i32, i32 } %call, 1
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%v6 = extractvalue { i32, i32, i32, i32 } %call, 2
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%v7 = extractvalue { i32, i32, i32, i32 } %call, 3
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%add = add nsw i32 %v3, %v5
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%add1 = add nsw i32 %add, %v6
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%add2 = add nsw i32 %add1, %v7
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ret i32 %add2
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}
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declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key)
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