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Add AVX matching patterns to Packed Bit Test intrinsics.
Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.
This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.
llvm-svn: 110744
This commit is contained in:
Bruno Cardoso Lopes
parent
a095d3fe73
commit
6eb24fd744
@ -6987,24 +6987,58 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
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DAG.getConstant(X86CC, MVT::i8), Cond);
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return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
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}
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// ptest intrinsics. The intrinsic these come from are designed to return
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// an integer value, not just an instruction so lower it to the ptest
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// pattern and a setcc for the result.
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// ptest and testp intrinsics. The intrinsic these come from are designed to
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// return an integer value, not just an instruction so lower it to the ptest
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// or testp pattern and a setcc for the result.
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case Intrinsic::x86_sse41_ptestz:
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case Intrinsic::x86_sse41_ptestc:
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case Intrinsic::x86_sse41_ptestnzc:{
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case Intrinsic::x86_sse41_ptestnzc:
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case Intrinsic::x86_avx_ptestz_256:
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case Intrinsic::x86_avx_ptestc_256:
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case Intrinsic::x86_avx_ptestnzc_256:
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case Intrinsic::x86_avx_vtestz_ps:
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case Intrinsic::x86_avx_vtestc_ps:
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case Intrinsic::x86_avx_vtestnzc_ps:
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case Intrinsic::x86_avx_vtestz_pd:
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case Intrinsic::x86_avx_vtestc_pd:
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case Intrinsic::x86_avx_vtestnzc_pd:
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case Intrinsic::x86_avx_vtestz_ps_256:
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case Intrinsic::x86_avx_vtestc_ps_256:
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case Intrinsic::x86_avx_vtestnzc_ps_256:
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case Intrinsic::x86_avx_vtestz_pd_256:
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case Intrinsic::x86_avx_vtestc_pd_256:
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case Intrinsic::x86_avx_vtestnzc_pd_256: {
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bool IsTestPacked = false;
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unsigned X86CC = 0;
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switch (IntNo) {
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default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
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case Intrinsic::x86_avx_vtestz_ps:
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case Intrinsic::x86_avx_vtestz_pd:
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case Intrinsic::x86_avx_vtestz_ps_256:
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case Intrinsic::x86_avx_vtestz_pd_256:
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IsTestPacked = true; // Fallthrough
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case Intrinsic::x86_sse41_ptestz:
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case Intrinsic::x86_avx_ptestz_256:
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// ZF = 1
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X86CC = X86::COND_E;
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break;
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case Intrinsic::x86_avx_vtestc_ps:
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case Intrinsic::x86_avx_vtestc_pd:
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case Intrinsic::x86_avx_vtestc_ps_256:
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case Intrinsic::x86_avx_vtestc_pd_256:
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IsTestPacked = true; // Fallthrough
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case Intrinsic::x86_sse41_ptestc:
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case Intrinsic::x86_avx_ptestc_256:
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// CF = 1
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X86CC = X86::COND_B;
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break;
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case Intrinsic::x86_avx_vtestnzc_ps:
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case Intrinsic::x86_avx_vtestnzc_pd:
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case Intrinsic::x86_avx_vtestnzc_ps_256:
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case Intrinsic::x86_avx_vtestnzc_pd_256:
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IsTestPacked = true; // Fallthrough
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case Intrinsic::x86_sse41_ptestnzc:
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case Intrinsic::x86_avx_ptestnzc_256:
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// ZF and CF = 0
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X86CC = X86::COND_A;
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break;
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@ -7012,7 +7046,8 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
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SDValue LHS = Op.getOperand(1);
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SDValue RHS = Op.getOperand(2);
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SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
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unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
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SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
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SDValue CC = DAG.getConstant(X86CC, MVT::i8);
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SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
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return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
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@ -8033,6 +8068,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::AND: return "X86ISD::AND";
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case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
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case X86ISD::PTEST: return "X86ISD::PTEST";
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case X86ISD::TESTP: return "X86ISD::TESTP";
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case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
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case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
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}
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@ -248,6 +248,9 @@ namespace llvm {
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// PTEST - Vector bitwise comparisons
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PTEST,
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// TESTP - Vector packed fp sign bitwise comparisons
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TESTP,
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// VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
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// according to %al. An operator is needed so that this can be expanded
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// with control flow.
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@ -117,9 +117,10 @@ def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
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def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
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def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
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SDTCisVT<1, v4f32>,
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SDTCisVT<2, v4f32>]>;
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SDTCisVec<1>,
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SDTCisSameAs<2, 1>]>;
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def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
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def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
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//===----------------------------------------------------------------------===//
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// SSE Complex Patterns
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@ -4646,47 +4646,52 @@ defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
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// the intel intrinsic that corresponds to this.
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let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
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def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
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"vptest\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
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OpSize, VEX;
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def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
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"vptest\t{$src2, $src1|$src1, $src2}", []>, OpSize, VEX;
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"vptest\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
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OpSize, VEX;
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def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
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"vptest\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
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OpSize, VEX;
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def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
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"vptest\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
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OpSize, VEX;
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def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
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"vptest\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
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OpSize, VEX;
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def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
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"vptest\t{$src2, $src1|$src1, $src2}", []>, OpSize, VEX;
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"vptest\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
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OpSize, VEX;
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}
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let Defs = [EFLAGS] in {
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def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
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"ptest \t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
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"ptest \t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
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OpSize;
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def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
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"ptest \t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
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def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
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"ptest \t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
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OpSize;
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}
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// The bit test instructions below are AVX only
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multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
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X86MemOperand x86memop> {
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def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[]>, OpSize, VEX;
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def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[]>, OpSize, VEX;
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X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
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def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
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[(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
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def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
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[(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
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OpSize, VEX;
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}
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let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
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defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem>;
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defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem>;
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defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem>;
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defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem>;
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defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
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defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
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defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
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defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
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}
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//===----------------------------------------------------------------------===//
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