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[FastISel][ARM] Fix a think-o in my previous commit (r215682).

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We actually need to return the register into which we materialized the constant
and not just "true" for success. This code is currently partially dead, that is
why it didn't trigger any failures yet. Once I change the order of the constant
materialization this code will be fully exercised.

llvm-svn: 215727
This commit is contained in:
Juergen Ributzka 2014-08-15 16:59:46 +00:00
parent f8bee1313e
commit 6ee8660aa9
1 changed files with 15 additions and 15 deletions
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24
lib/Target/ARM/ARMFastISel.cpp
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@ -513,7 +513,7 @@ unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
return false;
return 0;
// If we can do this in a single instruction without a constant pool entry
// do so now.
@ -546,15 +546,16 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
}
}
unsigned ResultReg = 0;
if (Subtarget->useMovt(*FuncInfo.MF))
if (FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()))
return true;
ResultReg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
if (ResultReg)
return ResultReg;
// Load from constant pool. For now 32-bit only.
if (VT != MVT::i32)
return false;
unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
return 0;
// MachineConstantPool wants an explicit alignment.
unsigned Align = DL.getPrefTypeAlignment(C->getType());
@ -563,21 +564,20 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
Align = DL.getTypeAllocSize(C->getType());
}
unsigned Idx = MCP.getConstantPoolIndex(C, Align);
ResultReg = createResultReg(TLI.getRegClassFor(VT));
if (isThumb2)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(ARM::t2LDRpci), DestReg)
TII.get(ARM::t2LDRpci), ResultReg)
.addConstantPoolIndex(Idx));
else {
// The extra immediate is for addrmode2.
DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(ARM::LDRcp), DestReg)
TII.get(ARM::LDRcp), ResultReg)
.addConstantPoolIndex(Idx)
.addImm(0));
}
return DestReg;
return ResultReg;
}
unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {