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[PPC] cleanup of mayLoad/mayStore flags and memory operands.
1) Explicitly sets mayLoad/mayStore property in the tablegen files on load/store
instructions.
2) Updated the flags on a number of intrinsics indicating that they write
memory.
3) Added SDNPMemOperand flags for some target dependent SDNodes so that they
propagate their memory operand
Review: https://reviews.llvm.org/D28818
llvm-svn: 293200
This commit is contained in:
Sean Fertile
parent
0ac47a0236
commit
6ef8fab619
@ -203,19 +203,19 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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// source address with a single pointer.
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def int_ppc_altivec_stvx :
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
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[IntrArgMemOnly]>;
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[IntrWriteMem, IntrArgMemOnly]>;
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def int_ppc_altivec_stvxl :
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
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[IntrArgMemOnly]>;
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[IntrWriteMem, IntrArgMemOnly]>;
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def int_ppc_altivec_stvebx :
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Intrinsic<[], [llvm_v16i8_ty, llvm_ptr_ty],
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[IntrArgMemOnly]>;
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[IntrWriteMem, IntrArgMemOnly]>;
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def int_ppc_altivec_stvehx :
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Intrinsic<[], [llvm_v8i16_ty, llvm_ptr_ty],
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[IntrArgMemOnly]>;
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[IntrWriteMem, IntrArgMemOnly]>;
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def int_ppc_altivec_stvewx :
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
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[IntrArgMemOnly]>;
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[IntrWriteMem, IntrArgMemOnly]>;
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// Comparisons setting a vector.
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def int_ppc_altivec_vcmpbfp : GCCBuiltin<"__builtin_altivec_vcmpbfp">,
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@ -749,20 +749,20 @@ def int_ppc_vsx_lxvll :
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IntrArgMemOnly]>;
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def int_ppc_vsx_stxvl :
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
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[IntrArgMemOnly]>;
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[IntrWriteMem, IntrArgMemOnly]>;
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def int_ppc_vsx_stxvll :
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
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[IntrArgMemOnly]>;
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[IntrWriteMem, IntrArgMemOnly]>;
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// Vector store.
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def int_ppc_vsx_stxvw4x :
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty], [IntrArgMemOnly]>;
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def int_ppc_vsx_stxvd2x :
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Intrinsic<[], [llvm_v2f64_ty, llvm_ptr_ty], [IntrArgMemOnly]>;
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def int_ppc_vsx_stxvw4x_be :
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty], [IntrArgMemOnly]>;
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def int_ppc_vsx_stxvd2x_be :
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Intrinsic<[], [llvm_v2f64_ty, llvm_ptr_ty], [IntrArgMemOnly]>;
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def int_ppc_vsx_stxvw4x : Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
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[IntrWriteMem, IntrArgMemOnly]>;
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def int_ppc_vsx_stxvd2x : Intrinsic<[], [llvm_v2f64_ty, llvm_ptr_ty],
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[IntrWriteMem, IntrArgMemOnly]>;
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def int_ppc_vsx_stxvw4x_be : Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
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[IntrWriteMem, IntrArgMemOnly]>;
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def int_ppc_vsx_stxvd2x_be : Intrinsic<[], [llvm_v2f64_ty, llvm_ptr_ty],
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[IntrWriteMem, IntrArgMemOnly]>;
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// Vector and scalar maximum.
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def int_ppc_vsx_xvmaxdp : PowerPC_VSX_Vec_DDD_Intrinsic<"xvmaxdp">;
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def int_ppc_vsx_xvmaxsp : PowerPC_VSX_Vec_FFF_Intrinsic<"xvmaxsp">;
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@ -953,7 +953,7 @@ class PowerPC_QPX_LoadPerm_Intrinsic<string GCCIntSuffix>
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class PowerPC_QPX_Store_Intrinsic<string GCCIntSuffix>
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: PowerPC_QPX_Intrinsic<GCCIntSuffix,
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[], [llvm_v4f64_ty, llvm_ptr_ty],
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[IntrArgMemOnly]>;
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[IntrWriteMem, IntrArgMemOnly]>;
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//===----------------------------------------------------------------------===//
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// PowerPC QPX Intrinsic Definitions.
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@ -2964,7 +2964,11 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
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SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
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SDValue Chain = LD->getChain();
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SDValue Ops[] = { Base, Offset, Chain };
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CurDAG->SelectNodeTo(N, PPC::LXVDSX, N->getValueType(0), Ops);
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SDNode *NewN = CurDAG->SelectNodeTo(N, PPC::LXVDSX,
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N->getValueType(0), Ops);
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = LD->getMemOperand();
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cast<MachineSDNode>(NewN)->setMemRefs(MemOp, MemOp + 1);
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return;
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}
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}
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@ -253,11 +253,11 @@ def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
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Requires<[IsISA3_0]>;
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}
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let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in
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let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
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def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
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"stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT;
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let mayStore = 1, hasSideEffects = 0 in
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let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
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def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
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"stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
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Requires<[IsISA3_0]>;
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@ -1082,7 +1082,7 @@ def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
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}
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// Stores with Update (pre-inc).
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let PPC970_Unit = 2, mayStore = 1 in {
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let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
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"stbu $rS, $dst", IIC_LdStStoreUpd, []>,
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@ -407,7 +407,7 @@ def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
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"mtvscr $vB", IIC_LdStLoad,
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[(int_ppc_altivec_mtvscr v4i32:$vB)]>;
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let PPC970_Unit = 2 in { // Loads.
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let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads.
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def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src),
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"lvebx $vD, $src", IIC_LdStLoad,
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[(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
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@ -434,7 +434,7 @@ def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src),
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[(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
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PPC970_Unit_LSU;
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let PPC970_Unit = 2 in { // Stores.
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let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores.
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def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
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"stvebx $rS, $dst", IIC_LdStStore,
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[(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
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@ -114,9 +114,9 @@ def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
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def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
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[SDNPHasChain, SDNPMayStore]>;
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def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
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[SDNPHasChain, SDNPMayLoad]>;
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
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[SDNPHasChain, SDNPMayLoad]>;
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx,
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[SDNPHasChain, SDNPMayLoad]>;
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def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix,
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@ -243,7 +243,7 @@ def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
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[SDNPHasChain, SDNPOptInGlue]>;
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def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
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[SDNPHasChain, SDNPMayLoad]>;
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
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[SDNPHasChain, SDNPMayStore]>;
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@ -1642,7 +1642,7 @@ let usesCustomInserter = 1 in {
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}
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// Instructions to support atomic operations
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let mayLoad = 1, hasSideEffects = 0 in {
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let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
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def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
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"lbarx $rD, $src", IIC_LdStLWARX, []>,
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Requires<[HasPartwordAtomics]>;
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@ -1675,7 +1675,7 @@ def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
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Requires<[IsISA3_0]>;
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}
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let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
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let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
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def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
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"stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
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isDOT, Requires<[HasPartwordAtomics]>;
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@ -1688,7 +1688,7 @@ def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
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"stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
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}
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let mayStore = 1, hasSideEffects = 0 in
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let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
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def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
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"stwat $rS, $rA, $FC", IIC_LdStStore>,
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Requires<[IsISA3_0]>;
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@ -1734,7 +1734,7 @@ def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
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// Unindexed (r+i) Loads with Update (preinc).
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let mayLoad = 1, hasSideEffects = 0 in {
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let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
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def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
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"lbzu $rD, $addr", IIC_LdStLoadUpd,
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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@ -1807,7 +1807,7 @@ def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
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// Indexed (r+r) Loads.
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//
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let PPC970_Unit = 2 in {
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let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in {
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def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
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"lbzx $rD, $src", IIC_LdStLoad,
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[(set i32:$rD, (zextloadi8 xaddr:$src))]>;
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@ -1821,8 +1821,6 @@ def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
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def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
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"lwzx $rD, $src", IIC_LdStLoad,
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[(set i32:$rD, (load xaddr:$src))]>;
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def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
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"lhbrx $rD, $src", IIC_LdStLoad,
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[(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
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@ -1854,7 +1852,7 @@ def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
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//
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// Unindexed (r+i) Stores.
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let PPC970_Unit = 2 in {
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let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
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def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
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"stb $rS, $src", IIC_LdStStore,
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[(truncstorei8 i32:$rS, iaddr:$src)]>;
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@ -1873,7 +1871,7 @@ def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
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}
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// Unindexed (r+i) Stores with Update (preinc).
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let PPC970_Unit = 2, mayStore = 1 in {
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let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
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def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
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"stbu $rS, $dst", IIC_LdStStoreUpd, []>,
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RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
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@ -1942,7 +1940,7 @@ def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
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}
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// Indexed (r+r) Stores with Update (preinc).
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let PPC970_Unit = 2, mayStore = 1 in {
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let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
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def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
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"stbux $rS, $dst", IIC_LdStStoreUpd, []>,
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RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
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@ -62,7 +62,7 @@ def SDTVecConv : SDTypeProfile<1, 2, [
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]>;
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def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
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[SDNPHasChain, SDNPMayLoad]>;
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,
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[SDNPHasChain, SDNPMayStore]>;
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def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
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@ -117,7 +117,7 @@ let hasSideEffects = 0 in { // VSX instructions don't have side effects.
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let Uses = [RM] in {
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// Load indexed instructions
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let mayLoad = 1 in {
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let mayLoad = 1, mayStore = 0 in {
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let CodeSize = 3 in
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def LXSDX : XX1Form<31, 588,
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(outs vsfrc:$XT), (ins memrr:$src),
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@ -142,7 +142,7 @@ let Uses = [RM] in {
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} // mayLoad
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// Store indexed instructions
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let mayStore = 1 in {
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let mayStore = 1, mayLoad = 0 in {
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let CodeSize = 3 in
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def STXSDX : XX1Form<31, 716,
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(outs), (ins vsfrc:$XT, memrr:$dst),
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@ -1197,7 +1197,7 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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[(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
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// VSX scalar loads introduced in ISA 2.07
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let mayLoad = 1 in {
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let mayLoad = 1, mayStore = 0 in {
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let CodeSize = 3 in
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def LXSSPX : XX1Form<31, 524, (outs vssrc:$XT), (ins memrr:$src),
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"lxsspx $XT, $src", IIC_LdStLFD,
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@ -1211,7 +1211,7 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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} // mayLoad
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// VSX scalar stores introduced in ISA 2.07
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let mayStore = 1 in {
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let mayStore = 1, mayLoad = 0 in {
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let CodeSize = 3 in
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def STXSSPX : XX1Form<31, 652, (outs), (ins vssrc:$XT, memrr:$dst),
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"stxsspx $XT, $dst", IIC_LdStSTFD,
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@ -2335,7 +2335,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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// When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
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// PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
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let mayLoad = 1 in {
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let mayLoad = 1, mayStore = 0 in {
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// Load Vector
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def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src),
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"lxv $XT, $src", IIC_LdStLFD, []>, UseVSXReg;
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@ -2383,7 +2383,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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// When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
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// PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
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let mayStore = 1 in {
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let mayStore = 1, mayLoad = 0 in {
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// Store Vector
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def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst),
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"stxv $XT, $dst", IIC_LdStSTFD, []>, UseVSXReg;
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@ -11,11 +11,11 @@
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; CHECK-LABEL: @zg
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; CHECK: xxspltd
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; CHECK-NEXT: xxspltd
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; CHECK-NEXT: xxswapd
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; CHECK-NEXT: xvmuldp
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; CHECK-NEXT: xvmuldp
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; CHECK-NEXT: xvsubdp
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; CHECK-NEXT: xvadddp
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; CHECK-NEXT: xxswapd
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; CHECK-NEXT: xxpermdi
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; CHECK-NEXT: xvsubdp
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; CHECK-NEXT: xxswapd
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@ -52,4 +52,4 @@ L.JA291:
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ret void
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}
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attributes #0 = { noinline }
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attributes #0 = { noinline }
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