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[AArch64] Simplify the scheduling predicates (NFC)

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The instruction encodings make it unnecessary to distinguish extended W-form
from X-form instructions.

llvm-svn: 349185
This commit is contained in:
Evandro Menezes 2018-12-14 20:04:58 +00:00
parent 7937eed98d
commit 6f096d4f5a
2 changed files with 21 additions and 17 deletions
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30
lib/Target/AArch64/AArch64SchedPredExynos.td
View File

@ -35,21 +35,13 @@ def ExynosExtFn : TIIPredicate<
"isExynosExtFast",
MCOpcodeSwitchStatement<
[MCOpcodeSwitchCase<
IsArithExt32Op.ValidOpcodes,
IsArithExtOp.ValidOpcodes,
MCReturnStatement<
CheckAny<[CheckExtBy0,
CheckAll<
[CheckExtUXTW,
CheckAny<
[CheckExtBy1,
CheckExtBy2,
CheckExtBy3]>]>]>>>,
MCOpcodeSwitchCase<
IsArithExt64Op.ValidOpcodes,
MCReturnStatement<
CheckAny<[CheckExtBy0,
CheckAll<
[CheckExtUXTX,
[CheckAny<
[CheckExtUXTW,
CheckExtUXTX]>,
CheckAny<
[CheckExtBy1,
CheckExtBy2,
@ -57,6 +49,20 @@ def ExynosExtFn : TIIPredicate<
MCReturnStatement<FalsePred>>>;
def ExynosExtPred : MCSchedPredicate<ExynosExtFn>;
// Identify a load or store using the register offset addressing mode
// with a scaled non-extended register.
def ExynosScaledIdxFn : TIIPredicate<"isExynosScaledAddr",
MCOpcodeSwitchStatement<
[MCOpcodeSwitchCase<
IsLoadStoreRegOffsetOp.ValidOpcodes,
MCReturnStatement<
CheckAny<
[CheckMemExtSXTW,
CheckMemExtUXTW,
CheckMemScaled]>>>],
MCReturnStatement<FalsePred>>>;
def ExynosScaledIdxPred : MCSchedPredicate<ExynosScaledIdxFn>;
// Identify FP instructions.
def ExynosFPPred : MCSchedPredicate<CheckAny<[CheckDForm, CheckQForm]>>;

8
lib/Target/AArch64/AArch64SchedPredicates.td
View File

@ -132,12 +132,10 @@ def CheckQForm : CheckAll<[CheckIsRegOperand<0>,
CheckRegOperand<0, Q31>]>]>;
// Identify arithmetic instructions with extend.
def IsArithExt32Op : CheckOpcode<[ADDWrx, ADDXrx, ADDSWrx, ADDSXrx,
SUBWrx, SUBXrx, SUBSWrx, SUBSXrx]>;
def IsArithExt64Op : CheckOpcode<[ADDXrx64, ADDSXrx64,
def IsArithExtOp : CheckOpcode<[ADDWrx, ADDXrx, ADDSWrx, ADDSXrx,
SUBWrx, SUBXrx, SUBSWrx, SUBSXrx,
ADDXrx64, ADDSXrx64,
SUBXrx64, SUBSXrx64]>;
def IsArithExtOp : CheckOpcode<!listconcat(IsArithExt32Op.ValidOpcodes,
IsArithExt64Op.ValidOpcodes)>;
// Identify arithmetic immediate instructions.
def IsArithImmOp : CheckOpcode<[ADDWri, ADDXri, ADDSWri, ADDSXri,