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Nice tasty llc fixes. These should fix LLC for x86 for everything in

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SingleSource except oopack and Oscar.  (Sorry, Oscar.)

include/llvm/Target/TargetInstrInfo.h: Remove virtual print method. Add
 accessors for ImplicitUses/Defs.
lib/Target/TargetInstrInfo.cpp: Remove virtual print method. If you
 really wanted this, just use MI->print(O, TM); instead...
lib/Target/X86:
FloatingPoint.cpp: ...like this.
X86InstrInfo.h: Remove virtual print method. Define the PrintImplUses
 target-specific flag bit.
X86InstrInfo.def: Add the PrintImplUses flag to all the instructions
 which implicitly use CL, because the assembler needs to see the CL in
 order to generate the right instruction.
Printer.cpp: Ditch fnIndex at Chris's request. Now we use CurrentFnName
  to name constants in the constant pool for each function instead. This
  avoids keeping state between runOnMachineFunction() invocations, which
  is a no-no. Having MangledGlobals be global is a bogon I'd like to get
  rid of too, but making it a static member of Printer causes link errors
  (why???).
 Make NumberForBB into a member of Printer instead of a global, too.
 Make printOp and printMemReference into methods of Printer.
 X86InstrInfo::print is now Printer::printMachineInstruction, because
  TargetInstrInfo::print is history. (Because of this, we have to qualify
  the names of some TargetInstrInfo methods we call.)
 Print out the ImplicitUses field of any instruction we print that has
  the PrintImplUses bit set.

llvm-svn: 6924
This commit is contained in:
Brian Gaeke 2003-06-27 00:00:48 +00:00
parent 40d8d5e7c5
commit 6f2c46cd52
6 changed files with 89 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
include/llvm/Target/TargetInstrInfo.h
View File

@ -109,13 +109,6 @@ public:
return desc[opCode];
}
/// print - Print out the specified machine instruction in the appropriate
/// target specific assembly language. If this method is not overridden, the
/// default implementation uses the crummy machine independant printer.
///
virtual void print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const;
const char *getName(MachineOpCode opCode) const {
return get(opCode).Name;
}
@ -135,7 +128,15 @@ public:
InstrSchedClass getSchedClass(MachineOpCode opCode) const {
return get(opCode).schedClass;
}
const unsigned *getImplicitUses(MachineOpCode opCode) const {
return get(opCode).ImplicitUses;
}
const unsigned *getImplicitDefs(MachineOpCode opCode) const {
return get(opCode).ImplicitDefs;
}
//
// Query instruction class flags according to the machine-independent
// flags listed above.

5
lib/Target/TargetInstrInfo.cpp
View File

@ -28,11 +28,6 @@ TargetInstrInfo::~TargetInstrInfo() {
TargetInstrDescriptors = NULL; // reset global variable
}
void TargetInstrInfo::print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const {
MI->print(O, TM);
}
bool TargetInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
int64_t intValue) const {
// First, check if opCode has an immed field.

4
lib/Target/X86/FloatingPoint.cpp
View File

@ -196,8 +196,8 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
MachineBasicBlock::iterator Start = I;
// Rewind to first instruction newly inserted.
while (Start != BB.begin() && *(Start-1) != PrevMI) --Start;
std::cerr << "Inserted instructions:\n";
do TII.print(*Start, std::cerr << "\t", MF.getTarget());
std::cerr << "Inserted instructions:\n\t";
(*Start)->print(std::cerr, MF.getTarget());
while (++Start != I+1);
}
dumpStack();

106
lib/Target/X86/Printer.cpp
View File

@ -24,16 +24,25 @@
#include "llvm/Module.h"
namespace {
unsigned fnIndex;
std::set<const Value*> MangledGlobals;
std::set<const Value *> MangledGlobals;
struct Printer : public MachineFunctionPass {
std::ostream &O;
typedef std::map<const Value *, unsigned> ValueMapTy;
ValueMapTy NumberForBB;
Printer(std::ostream &o) : O(o) {}
const TargetData *TD;
std::string CurrentFnName;
virtual const char *getPassName() const {
return "X86 Assembly Printer";
}
void printMachineInstruction(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const;
void printOp(std::ostream &O, const MachineOperand &MO,
const MRegisterInfo &RI, bool elideOffsetKeyword = false) const;
void printMemReference(std::ostream &O, const MachineInstr *MI,
unsigned Op,
const MRegisterInfo &RI) const;
void printConstantPool(MachineConstantPool *MCP);
bool runOnMachineFunction(MachineFunction &F);
std::string ConstantExprToString(const ConstantExpr* CE);
@ -44,8 +53,7 @@ namespace {
void printConstantValueOnly(const Constant* CV, int numPadBytesAfter = 0);
void printSingleConstantValue(const Constant* CV);
};
std::map<const Value *, unsigned> NumberForBB;
}
} // end of anonymous namespace
/// createX86CodePrinterPass - Print out the specified machine code function to
/// the specified stream. This function should work regardless of whether or
@ -55,8 +63,8 @@ Pass *createX86CodePrinterPass(std::ostream &O) {
return new Printer(O);
}
// We dont want identifier names with ., space, - in them.
// So we replace them with _
// We don't want identifier names with ., space, or - in them,
// so we replace them with underscores.
static std::string makeNameProper(std::string x) {
std::string tmp;
for (std::string::iterator sI = x.begin(), sEnd = x.end(); sI != sEnd; sI++)
@ -66,38 +74,32 @@ static std::string makeNameProper(std::string x) {
case '-': tmp += "D_"; break;
default: tmp += *sI;
}
return tmp;
}
std::string getValueName(const Value *V) {
static std::string getValueName(const Value *V) {
if (V->hasName()) { // Print out the label if it exists...
// Name mangling occurs as follows:
// - If V is not a global, mangling always occurs.
// - Otherwise, mangling occurs when any of the following are true:
// 1) V has internal linkage
// 2) V's name would collide if it is not mangled.
//
if(const GlobalValue* gv = dyn_cast<GlobalValue>(V)) {
if(!gv->hasInternalLinkage() && !MangledGlobals.count(gv)) {
// No internal linkage, name will not collide -> no mangling.
return makeNameProper(gv->getName());
}
}
// Non-global, or global with internal linkage / colliding name -> mangle.
return "l" + utostr(V->getType()->getUniqueID()) + "_" +
makeNameProper(V->getName());
}
static int Count = 0;
Count++;
return "ltmp_" + itostr(Count) + "_" + utostr(V->getType()->getUniqueID());
}
// valToExprString - Helper function for ConstantExprToString().
// Appends result to argument string S.
//
@ -391,7 +393,8 @@ void Printer::printConstantPool(MachineConstantPool *MCP){
O << "\t.section .rodata\n";
O << "\t.align " << (unsigned)TD->getTypeAlignment(CP[i]->getType())
<< "\n";
O << ".CPI" << fnIndex << "_" << i << ":\t\t\t\t\t#" << *CP[i] << "\n";
O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t#"
<< *CP[i] << "\n";
printConstantValueOnly (CP[i]);
}
}
@ -404,16 +407,21 @@ bool Printer::runOnMachineFunction(MachineFunction &MF) {
const TargetInstrInfo &TII = TM.getInstrInfo();
TD = &TM.getTargetData();
// What's my mangled name?
CurrentFnName = getValueName(MF.getFunction());
// Print out constants referenced by the function
printConstantPool(MF.getConstantPool());
// Print out labels for the function.
O << "\t.text\n";
O << "\t.align 16\n";
O << "\t.globl\t" << getValueName(MF.getFunction()) << "\n";
O << "\t.type\t" << getValueName(MF.getFunction()) << ", @function\n";
O << getValueName(MF.getFunction()) << ":\n";
O << "\t.globl\t" << CurrentFnName << "\n";
O << "\t.type\t" << CurrentFnName << ", @function\n";
O << CurrentFnName << ":\n";
// Number each basic block so that we can consistently refer to them
// in PC-relative references.
NumberForBB.clear();
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
@ -430,11 +438,10 @@ bool Printer::runOnMachineFunction(MachineFunction &MF) {
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
TII.print(*II, O, TM);
printMachineInstruction(*II, O, TM);
}
}
fnIndex++;
// We didn't modify anything.
return false;
}
@ -453,8 +460,9 @@ static bool isMem(const MachineInstr *MI, unsigned Op) {
MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
}
static void printOp(std::ostream &O, const MachineOperand &MO,
const MRegisterInfo &RI, bool elideOffsetKeyword = false) {
void Printer::printOp(std::ostream &O, const MachineOperand &MO,
const MRegisterInfo &RI,
bool elideOffsetKeyword /* = false */) const {
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (Value *V = MO.getVRegValueOrNull()) {
@ -474,8 +482,12 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
O << (int)MO.getImmedValue();
return;
case MachineOperand::MO_PCRelativeDisp:
O << ".BB" << NumberForBB[MO.getVRegValue()] << " # PC rel: "
<< MO.getVRegValue()->getName();
{
ValueMapTy::const_iterator i = NumberForBB.find(MO.getVRegValue());
assert (i != NumberForBB.end()
&& "Could not find a BB I previously put in the NumberForBB map!");
O << ".BB" << i->second << " # PC rel: " << MO.getVRegValue()->getName();
}
return;
case MachineOperand::MO_GlobalAddress:
if (!elideOffsetKeyword) O << "OFFSET "; O << getValueName(MO.getGlobal());
@ -501,8 +513,9 @@ static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
}
}
static void printMemReference(std::ostream &O, const MachineInstr *MI,
unsigned Op, const MRegisterInfo &RI) {
void Printer::printMemReference(std::ostream &O, const MachineInstr *MI,
unsigned Op,
const MRegisterInfo &RI) const {
assert(isMem(MI, Op) && "Invalid memory reference!");
if (MI->getOperand(Op).isFrameIndex()) {
@ -512,7 +525,7 @@ static void printMemReference(std::ostream &O, const MachineInstr *MI,
O << "]";
return;
} else if (MI->getOperand(Op).isConstantPoolIndex()) {
O << "[.CPI" << fnIndex << "_"
O << "[.CPI" << CurrentFnName << "_"
<< MI->getOperand(Op).getConstantPoolIndex();
if (MI->getOperand(Op+3).getImmedValue())
O << " + " << MI->getOperand(Op+3).getImmedValue();
@ -553,11 +566,14 @@ static void printMemReference(std::ostream &O, const MachineInstr *MI,
O << "]";
}
// print - Print out an x86 instruction in intel syntax
void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const {
/// printMachineInstruction -- Print out an x86 instruction in intel syntax
///
void Printer::printMachineInstruction(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const {
unsigned Opcode = MI->getOpcode();
const TargetInstrDescriptor &Desc = get(Opcode);
const TargetInstrInfo &TII = TM.getInstrInfo();
const TargetInstrDescriptor &Desc = TII.get(Opcode);
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (Desc.TSFlags & X86II::FormMask) {
case X86II::Pseudo:
@ -584,7 +600,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
O << " = ";
++i;
}
O << getName(MI->getOpcode());
O << TII.getName(MI->getOpcode());
for (unsigned e = MI->getNumOperands(); i != e; ++i) {
O << " ";
@ -610,7 +626,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
MI->getOperand(0).isGlobalAddress() ||
MI->getOperand(0).isExternalSymbol())) &&
"Illegal raw instruction!");
O << getName(MI->getOpcode()) << " ";
O << TII.getName(MI->getOpcode()) << " ";
if (MI->getNumOperands() == 1) {
printOp(O, MI->getOperand(0), RI, true); // Don't print "OFFSET"...
@ -639,7 +655,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
unsigned Reg = MI->getOperand(0).getReg();
O << getName(MI->getOpCode()) << " ";
O << TII.getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
if (MI->getNumOperands() == 2 &&
(!MI->getOperand(1).isRegister() ||
@ -666,7 +682,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
// 4 Operands: This form is for instructions which are 3 operands forms, but
// have a constant argument as well.
//
bool isTwoAddr = isTwoAddrInstr(Opcode);
bool isTwoAddr = TII.isTwoAddrInstr(Opcode);
assert(MI->getOperand(0).isRegister() &&
(MI->getNumOperands() == 2 ||
(isTwoAddr && MI->getOperand(1).isRegister() &&
@ -675,7 +691,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
(MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate()))))
&& "Bad format for MRMDestReg!");
O << getName(MI->getOpCode()) << " ";
O << TII.getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
O << ", ";
printOp(O, MI->getOperand(1+isTwoAddr), RI);
@ -694,7 +710,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
O << getName(MI->getOpCode()) << " " << sizePtr(Desc) << " ";
O << TII.getName(MI->getOpCode()) << " " << sizePtr(Desc) << " ";
printMemReference(O, MI, 0, RI);
O << ", ";
printOp(O, MI->getOperand(4), RI);
@ -721,7 +737,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
O << "**";
O << getName(MI->getOpCode()) << " ";
O << TII.getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
O << ", ";
printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
@ -742,7 +758,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
O << "**";
O << getName(MI->getOpCode()) << " ";
O << TII.getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
O << ", " << sizePtr(Desc) << " ";
printMemReference(O, MI, MI->getNumOperands()-4, RI);
@ -773,12 +789,17 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
O << "**";
O << getName(MI->getOpCode()) << " ";
O << TII.getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
O << ", ";
printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
}
if (Desc.TSFlags & X86II::PrintImplUses) {
for (const unsigned *p = Desc.ImplicitUses; *p; ++p) {
O << ", " << RI.get(*p).Name;
}
}
O << "\n";
return;
@ -799,7 +820,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) &&
"Bad MRMSxM format!");
O << getName(MI->getOpCode()) << " ";
O << TII.getName(MI->getOpCode()) << " ";
O << sizePtr(Desc) << " ";
printMemReference(O, MI, 0, RI);
if (MI->getNumOperands() == 5) {
@ -821,9 +842,6 @@ bool Printer::doInitialization(Module &M)
// with no % decorations on register names.
O << "\t.intel_syntax noprefix\n";
// Start function index at 0
fnIndex = 0;
// Ripped from CWriter:
// Calculate which global values have names that will collide when we throw
// away type information.
@ -872,3 +890,5 @@ bool Printer::doFinalization(Module &M)
MangledGlobals.clear();
return false; // success
}

22
lib/Target/X86/X86InstrInfo.def
View File

@ -220,29 +220,29 @@ I(TESTrr32 , "test", 0x85, 0, X86II::MRMDestReg | X86II::Arg32, NoIR, NoIR)
// Shift instructions
I(SHLrr8 , "shl", 0xD2, M_2_ADDR_FLAG, X86II::MRMS4r, O_CL, NoIR) // R8 <<= cl
I(SHLrr16 , "shl", 0xD3, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::OpSize, O_CL, NoIR) // R16 <<= cl
I(SHLrr32 , "shl", 0xD3, M_2_ADDR_FLAG, X86II::MRMS4r, O_CL, NoIR) // R32 <<= cl
I(SHLrr8 , "shl", 0xD2, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::PrintImplUses, O_CL, NoIR) // R8 <<= cl
I(SHLrr16 , "shl", 0xD3, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::OpSize | X86II::PrintImplUses, O_CL, NoIR) // R16 <<= cl
I(SHLrr32 , "shl", 0xD3, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::PrintImplUses, O_CL, NoIR) // R32 <<= cl
I(SHLir8 , "shl", 0xC0, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8, NoIR, NoIR) // R8 <<= imm8
I(SHLir16 , "shl", 0xC1, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 <<= imm8
I(SHLir32 , "shl", 0xC1, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8, NoIR, NoIR) // R32 <<= imm8
I(SHRrr8 , "shr", 0xD2, M_2_ADDR_FLAG, X86II::MRMS5r, O_CL, NoIR) // R8 >>>= cl
I(SHRrr16 , "shr", 0xD3, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::OpSize, O_CL, NoIR) // R16 >>>= cl
I(SHRrr32 , "shr", 0xD3, M_2_ADDR_FLAG, X86II::MRMS5r, O_CL, NoIR) // R32 >>>= cl
I(SHRrr8 , "shr", 0xD2, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::PrintImplUses, O_CL, NoIR) // R8 >>>= cl
I(SHRrr16 , "shr", 0xD3, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::OpSize | X86II::PrintImplUses, O_CL, NoIR) // R16 >>>= cl
I(SHRrr32 , "shr", 0xD3, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::PrintImplUses, O_CL, NoIR) // R32 >>>= cl
I(SHRir8 , "shr", 0xC0, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8, NoIR, NoIR) // R8 >>>= imm8
I(SHRir16 , "shr", 0xC1, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 >>>= imm8
I(SHRir32 , "shr", 0xC1, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8, NoIR, NoIR) // R32 >>>= imm8
I(SARrr8 , "sar", 0xD2, M_2_ADDR_FLAG, X86II::MRMS7r, O_CL, NoIR) // R8 >>= cl
I(SARrr16 , "sar", 0xD3, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::OpSize, O_CL, NoIR) // R16 >>= cl
I(SARrr32 , "sar", 0xD3, M_2_ADDR_FLAG, X86II::MRMS7r, O_CL, NoIR) // R32 >>= cl
I(SARrr8 , "sar", 0xD2, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::PrintImplUses, O_CL, NoIR) // R8 >>= cl
I(SARrr16 , "sar", 0xD3, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::OpSize | X86II::PrintImplUses, O_CL, NoIR) // R16 >>= cl
I(SARrr32 , "sar", 0xD3, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::PrintImplUses, O_CL, NoIR) // R32 >>= cl
I(SARir8 , "sar", 0xC0, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // R8 >>= imm8
I(SARir16 , "sar", 0xC1, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 >>= imm8
I(SARir32 , "sar", 0xC1, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // R32 >>= imm8
I(SHLDir32 , "shld", 0xA4, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::TB | X86II::Arg8, NoIR, NoIR) // R32 >>= R32,R32 imm8
I(SHLDrr32 , "shld", 0xA5, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::TB, O_CL, NoIR) // R32 >>= R32,R32 cl
I(SHLDrr32 , "shld", 0xA5, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::TB | X86II::PrintImplUses, O_CL, NoIR) // R32 >>= R32,R32 cl
I(SHRDir32 , "shrd", 0xAC, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::TB | X86II::Arg8, NoIR, NoIR) // R32 >>= R32,R32 imm8
I(SHRDrr32 , "shrd", 0xAD, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::TB, O_CL, NoIR) // R32 >>= R32,R32 cl
I(SHRDrr32 , "shrd", 0xAD, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::TB | X86II::PrintImplUses, O_CL, NoIR) // R32 >>= R32,R32 cl
// Condition code ops, incl. set if equal/not equal/...

10
lib/Target/X86/X86InstrInfo.h
View File

@ -133,7 +133,10 @@ namespace X86II {
// FPTypeMask - Mask for all of the FP types...
FPTypeMask = 7 << 14,
// Bits 17 -> 31 are unused
// PrintImplUses - Print out implicit uses in the assembly output.
PrintImplUses = 1 << 17
// Bits 18 -> 31 are unused
};
}
@ -160,11 +163,6 @@ public:
///
bool isNOPinstr(const MachineInstr &MI) const;
/// print - Print out an x86 instruction in intel syntax
///
virtual void print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const;
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
// specified opcode number.
//