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[Hexagon] Ignore indexed loads when handling unaligned loads
llvm-svn: 327037
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1c17c0710c
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@ -2540,9 +2540,6 @@ HexagonTargetLowering::LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG)
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unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy);
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if (HaveAlign >= NeedAlign)
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return Op;
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// Indexed loads/stores are created after legalizing operations, so we
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// shouldn't be getting unaligned post-incrementing loads at this point.
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assert(LN->isUnindexed() && "Expecting only unindexed loads");
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const SDLoc &dl(Op);
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const DataLayout &DL = DAG.getDataLayout();
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@ -2552,6 +2549,10 @@ HexagonTargetLowering::LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG)
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// If the load aligning is disabled or the load can be broken up into two
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// smaller legal loads, do the default (target-independent) expansion.
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bool DoDefault = false;
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// Handle it in the default way if this is an indexed load.
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if (!LN->isUnindexed())
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DoDefault = true;
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if (!AlignLoads) {
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if (allowsMemoryAccess(Ctx, DL, LN->getMemoryVT(), AS, HaveAlign))
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return Op;
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@ -0,0 +1,67 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check for successful compilation.
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; CHECK: vmem
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target triple = "hexagon"
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; Function Attrs: nounwind
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define dso_local void @f0(i8* %a0, i8* %a1) local_unnamed_addr #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = phi i32 [ %v18, %b1 ], [ 0, %b0 ]
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%v1 = getelementptr inbounds i8, i8* %a1, i32 %v0
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%v2 = load <64 x i8>, <64 x i8>* undef, align 1, !tbaa !0, !alias.scope !3
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%v3 = add <64 x i8> zeroinitializer, %v2
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%v4 = getelementptr inbounds i8, i8* %a0, i32 undef
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%v5 = getelementptr inbounds i8, i8* %a0, i32 undef
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%v6 = getelementptr inbounds i8, i8* %a0, i32 undef
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store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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%v7 = extractelement <64 x i8> %v3, i32 12
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store i8 %v7, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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store i8 undef, i8* %v4, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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store i8 0, i8* %v5, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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%v8 = extractelement <64 x i8> %v3, i32 36
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store i8 %v8, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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%v9 = extractelement <64 x i8> %v3, i32 38
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store i8 %v9, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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%v10 = extractelement <64 x i8> %v3, i32 41
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store i8 %v10, i8* %v6, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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store i8 undef, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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%v11 = extractelement <64 x i8> %v3, i32 55
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store i8 %v11, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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%v12 = extractelement <64 x i8> %v3, i32 58
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store i8 %v12, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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%v13 = bitcast i8* %v1 to <64 x i8>*
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%v14 = load <64 x i8>, <64 x i8>* %v13, align 1, !tbaa !0, !alias.scope !3
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%v15 = add <64 x i8> zeroinitializer, %v14
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%v16 = getelementptr inbounds i8, i8* %a0, i32 undef
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%v17 = extractelement <64 x i8> %v15, i32 23
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store i8 %v17, i8* %v16, align 1, !tbaa !0, !alias.scope !6, !noalias !8
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%v18 = add i32 %v0, 64
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br label %b1
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"omnipotent char", !2, i64 0}
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!2 = !{!"Simple C/C++ TBAA"}
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!3 = !{!4}
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!4 = distinct !{!4, !5}
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!5 = distinct !{!5, !"LVerDomain"}
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!6 = !{!7}
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!7 = distinct !{!7, !5}
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!8 = !{!4, !9, !10, !11}
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!9 = distinct !{!9, !5}
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!10 = distinct !{!10, !5}
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!11 = distinct !{!11, !5}
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