From 6f59ec7d261c1cc3711f58d9860aa63b8bc701af Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Mon, 20 Apr 2020 18:43:52 -0700 Subject: [PATCH] [ARM] Fix MIR tests with invalid live-ins. A register can't be live if it isn't defined; fix issues in various testcases. Differential Revision: https://reviews.llvm.org/D78529 --- test/CodeGen/ARM/constant-islands-split-IT.mir | 2 -- test/CodeGen/ARM/ifcvt-size.mir | 2 +- .../CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir | 2 +- .../LowOverheadLoops/loop-dec-copy-prev-iteration.mir | 2 +- .../Thumb2/LowOverheadLoops/predicated-liveout.mir | 10 +++++----- .../Thumb2/LowOverheadLoops/safe-def-no-mov.mir | 2 +- .../Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir | 4 ++-- .../CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir | 2 +- .../Thumb2/LowOverheadLoops/unsafe-use-after.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir | 6 +++--- 10 files changed, 16 insertions(+), 18 deletions(-) diff --git a/test/CodeGen/ARM/constant-islands-split-IT.mir b/test/CodeGen/ARM/constant-islands-split-IT.mir index 82eee55b825..bbeae30ffec 100644 --- a/test/CodeGen/ARM/constant-islands-split-IT.mir +++ b/test/CodeGen/ARM/constant-islands-split-IT.mir @@ -110,7 +110,6 @@ body: | ; CHECK: CONSTPOOL_ENTRY 6, %const.0, 8 ; CHECK: bb.9 (align 2): ; CHECK: successors: %bb.9(0x80000000) - ; CHECK: liveins: $r0 ; CHECK: dead renamable $r0 = SPACE 4000, undef renamable $r0 ; CHECK: t2B %bb.9, 14 /* CC::al */, $noreg ; CHECK: bb.10: @@ -143,7 +142,6 @@ body: | bb.3: successors: %bb.3(0x80000000) - liveins: $r0 dead renamable $r0 = SPACE 4000, undef renamable $r0 t2B %bb.3, 14, $noreg diff --git a/test/CodeGen/ARM/ifcvt-size.mir b/test/CodeGen/ARM/ifcvt-size.mir index a5c31cbab4a..28391ba8079 100644 --- a/test/CodeGen/ARM/ifcvt-size.mir +++ b/test/CodeGen/ARM/ifcvt-size.mir @@ -369,7 +369,7 @@ body: | bb.1.if.then: successors: %bb.3(0x30000000), %bb.4(0x50000000) - liveins: $r0, $r3 + liveins: $r0, $r1, $r3 renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir b/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir index 3e302048d94..047701aaa75 100644 --- a/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir +++ b/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir @@ -140,7 +140,7 @@ body: | renamable $r12 = t2MOVi 4, 14, $noreg, $noreg tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr t2IT 11, 8, implicit-def $itstate - $r1 = t2ADDri killed renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate + $r1 = t2ADDri renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate $r3 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate $r12 = t2LSLri renamable $r3, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir b/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir index 7355de9236a..f59a322e143 100644 --- a/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir +++ b/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir @@ -410,7 +410,7 @@ body: | bb.5.bb28: successors: %bb.5(0x7c000000), %bb.6(0x04000000) - liveins: $r0, $r1, $r2, $r3, $r8, $r12, $lr + liveins: $r0, $r1, $r2, $r3, $r8, $lr renamable $r5 = tLDRr renamable $r1, $r3, 14, $noreg :: (load 4 from %ir.scevgep617) renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir b/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir index 3e5bda22732..966bdc913c4 100644 --- a/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir +++ b/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir @@ -80,7 +80,7 @@ body: | ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x40000000), %bb.4(0x40000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 @@ -104,7 +104,7 @@ body: | ; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: bb.4.for.cond.cleanup: - ; CHECK: liveins: $lr, $r7 + ; CHECK: liveins: $lr ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 bb.0.entry: @@ -117,7 +117,7 @@ body: | frame-setup CFI_INSTRUCTION offset $r7, -8 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg renamable $lr = t2LSRri killed renamable $r3, 3, 14, $noreg, $noreg - t2WhileLoopStart killed renamable $lr, %bb.4, implicit-def dead $cpsr + t2WhileLoopStart renamable $lr, %bb.4, implicit-def dead $cpsr tB %bb.1, 14, $noreg bb.1.for.body.preheader: @@ -140,7 +140,7 @@ body: | renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.input_1_cast, align 1) renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 1, renamable $vpr, undef renamable $q1 renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 1, killed renamable $vpr, undef renamable $q0 - t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr + t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg bb.3.middle.block: @@ -150,7 +150,7 @@ body: | tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 bb.4.for.cond.cleanup: - liveins: $lr, $r7 + liveins: $lr $r0, dead $cpsr = tMOVi8 0, 14, $noreg tBX_RET 14, $noreg, implicit killed $r0 diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir b/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir index ddc7c905098..20baa86fa1b 100644 --- a/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir +++ b/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir @@ -126,7 +126,7 @@ body: | bb.1.preheader: successors: %bb.2(0x80000000) - liveins: $r0 + liveins: $r0, $r1 $lr = tMOVr $r0, 14, $noreg bb.2.while.body: diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir b/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir index 53e31be78d7..475120a1ab6 100644 --- a/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir +++ b/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir @@ -131,7 +131,7 @@ body: | renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg t2DoLoopStart renamable $r0 renamable $r2 = t2LSRri renamable $r0, 1, 14, $noreg, $noreg - $lr = tMOVr killed $r0, 14, $noreg + $lr = tMOVr $r0, 14, $noreg bb.1.while.body: successors: %bb.1(0x7c000000), %bb.2(0x04000000) @@ -144,7 +144,7 @@ body: | renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4) renamable $lr = tMOVr $lr, 14, $noreg - t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr + t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14, $noreg bb.2.while.end: diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir b/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir index 2c96665e638..f39af6fb090 100644 --- a/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir +++ b/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir @@ -102,7 +102,7 @@ body: | bb.1.preheader: successors: %bb.2(0x80000000) - liveins: $r0, $lr + liveins: $r0, $r1, $lr $lr = tMOVr $r0, 14, $noreg bb.2.while.body: diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir b/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir index fa1c4f70d81..c0c04f997c3 100644 --- a/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir +++ b/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir @@ -125,7 +125,7 @@ body: | bb.1.preheader: successors: %bb.2(0x80000000) - liveins: $r0 + liveins: $r0, $r1 $lr = tMOVr $r0, 14, $noreg bb.2.while.body: diff --git a/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir b/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir index a2c722ed136..4ac7f1152d6 100644 --- a/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir +++ b/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir @@ -69,10 +69,10 @@ body: | ; CHECK: liveins: $q0, $q1, $q2, $r0 ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 - ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { + ; CHECK: BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 - ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 1, renamable $vpr, undef renamable $q1 + ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal renamable $q3, internal renamable $q3, 1, renamable $vpr, undef renamable $q1 ; CHECK: } ; CHECK: bb.1.bb2: ; CHECK: liveins: $q0, $q1, $q2, $q3, $vpr @@ -88,7 +88,7 @@ body: | $vpr = VMSR_P0 killed $r0, 14, $noreg $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 - renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1 + renamable $q1 = nnan ninf nsz MVE_VMINNMf32 renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1 bb.1.bb2: liveins: $q0, $q1, $q2, $q3, $vpr