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[ARM][MVE] Add HorizontalReduction flag
Add a target flag for instructions that reduce into one, or more, scalar reg(s), including variants of: - VADDV - VABAV - VMINV/VMAXV - VMLADAV Differential Revision: https://reviews.llvm.org/D76683
This commit is contained in:
Sam Parker
parent
bda88afd34
commit
6f6eed9671
@ -409,6 +409,7 @@ class InstTemplate<AddrMode am, int sz, IndexMode im,
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bit validForTailPredication = 0;
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bit retainsPreviousHalfElement = 0;
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bit horizontalReduction = 0;
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// If this is a pseudo instruction, mark it isCodeGenOnly.
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let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
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@ -423,6 +424,7 @@ class InstTemplate<AddrMode am, int sz, IndexMode im,
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let TSFlags{19} = thumbArithFlagSetting;
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let TSFlags{20} = validForTailPredication;
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let TSFlags{21} = retainsPreviousHalfElement;
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let TSFlags{22} = horizontalReduction;
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let Constraints = cstr;
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let Itinerary = itin;
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@ -556,6 +556,7 @@ class MVE_VABAV<string suffix, bit U, bits<2> size>
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let Inst{5} = Qm{3};
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let Inst{3-1} = Qm{2-0};
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let Inst{0} = 0b1;
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let horizontalReduction = 1;
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}
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multiclass MVE_VABAV_m<MVEVectorVTInfo VTI> {
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@ -605,6 +606,7 @@ class MVE_VADDV<string iname, string suffix, dag iops, string cstr,
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let Inst{5} = A;
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let Inst{3-1} = Qm{2-0};
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let Inst{0} = 0b0;
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let horizontalReduction = 1;
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}
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def ARMVADDVs : SDNode<"ARMISD::VADDVs", SDTVecReduce>;
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@ -678,6 +680,7 @@ class MVE_VADDLV<string iname, string suffix, dag iops, string cstr,
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let Inst{5} = A;
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let Inst{3-1} = Qm{2-0};
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let Inst{0} = 0b0;
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let horizontalReduction = 1;
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}
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def SDTVecReduceL : SDTypeProfile<2, 1, [ // VADDLV
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@ -749,6 +752,7 @@ class MVE_VMINMAXNMV<string iname, string suffix, bit sz,
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let Inst{6-5} = 0b00;
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let Inst{3-1} = Qm{2-0};
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let Inst{0} = 0b0;
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let horizontalReduction = 1;
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let Predicates = [HasMVEFloat];
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}
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@ -808,6 +812,7 @@ class MVE_VMINMAXV<string iname, string suffix, bit U, bits<2> size,
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let Inst{6-5} = 0b00;
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let Inst{3-1} = Qm{2-0};
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let Inst{0} = 0b0;
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let horizontalReduction = 1;
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}
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multiclass MVE_VMINMAXV_p<string iname, bit notAbs, bit isMin,
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@ -899,6 +904,7 @@ class MVE_VMLAMLSDAV<string iname, string suffix, dag iops, string cstr,
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let Inst{5} = A;
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let Inst{3-1} = Qm{2-0};
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let Inst{0} = bit_0;
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let horizontalReduction = 1;
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}
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multiclass MVE_VMLAMLSDAV_A<string iname, string x, MVEVectorVTInfo VTI,
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@ -1057,6 +1063,7 @@ class MVE_VMLALDAVBase<string iname, string suffix, dag iops, string cstr,
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let Inst{5} = A;
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let Inst{3-1} = Qm{2-0};
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let Inst{0} = bit_0;
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let horizontalReduction = 1;
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}
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multiclass MVE_VMLALDAVBase_A<string iname, string x, string suffix,
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@ -400,6 +400,9 @@ namespace ARMII {
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// and leaves the other half untouched.
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RetainsPreviousHalfElement = 1 << 21,
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// Whether the instruction produces a scalar result from vector operands.
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HorizontalReduction = 1 << 22,
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//===------------------------------------------------------------------===//
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// Code domain.
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DomainShift = 15,
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@ -10,6 +10,163 @@
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using namespace llvm;
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TEST(MachineInstructionHorizontalReduction, IsCorrect) {
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using namespace ARM;
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auto HorizontalReduction = [](unsigned Opcode) {
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switch (Opcode) {
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default:
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break;
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case MVE_VABAVs16:
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case MVE_VABAVs32:
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case MVE_VABAVs8:
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case MVE_VABAVu16:
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case MVE_VABAVu32:
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case MVE_VABAVu8:
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case MVE_VADDLVs32acc:
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case MVE_VADDLVs32no_acc:
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case MVE_VADDLVu32acc:
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case MVE_VADDLVu32no_acc:
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case MVE_VADDVs16acc:
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case MVE_VADDVs16no_acc:
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case MVE_VADDVs32acc:
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case MVE_VADDVs32no_acc:
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case MVE_VADDVs8acc:
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case MVE_VADDVs8no_acc:
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case MVE_VADDVu16acc:
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case MVE_VADDVu16no_acc:
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case MVE_VADDVu32acc:
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case MVE_VADDVu32no_acc:
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case MVE_VADDVu8acc:
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case MVE_VADDVu8no_acc:
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case MVE_VMAXAVs16:
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case MVE_VMAXAVs32:
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case MVE_VMAXAVs8:
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case MVE_VMAXNMAVf16:
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case MVE_VMAXNMAVf32:
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case MVE_VMAXNMVf16:
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case MVE_VMAXNMVf32:
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case MVE_VMAXVs16:
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case MVE_VMAXVs32:
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case MVE_VMAXVs8:
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case MVE_VMAXVu16:
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case MVE_VMAXVu32:
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case MVE_VMAXVu8:
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case MVE_VMINAVs16:
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case MVE_VMINAVs32:
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case MVE_VMINAVs8:
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case MVE_VMINNMAVf16:
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case MVE_VMINNMAVf32:
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case MVE_VMINNMVf16:
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case MVE_VMINNMVf32:
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case MVE_VMINVs16:
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case MVE_VMINVs32:
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case MVE_VMINVs8:
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case MVE_VMINVu16:
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case MVE_VMINVu32:
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case MVE_VMINVu8:
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case MVE_VMLADAVas16:
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case MVE_VMLADAVas32:
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case MVE_VMLADAVas8:
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case MVE_VMLADAVau16:
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case MVE_VMLADAVau32:
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case MVE_VMLADAVau8:
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case MVE_VMLADAVaxs16:
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case MVE_VMLADAVaxs32:
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case MVE_VMLADAVaxs8:
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case MVE_VMLADAVs16:
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case MVE_VMLADAVs32:
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case MVE_VMLADAVs8:
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case MVE_VMLADAVu16:
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case MVE_VMLADAVu32:
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case MVE_VMLADAVu8:
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case MVE_VMLADAVxs16:
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case MVE_VMLADAVxs32:
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case MVE_VMLADAVxs8:
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case MVE_VMLALDAVas16:
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case MVE_VMLALDAVas32:
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case MVE_VMLALDAVau16:
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case MVE_VMLALDAVau32:
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case MVE_VMLALDAVaxs16:
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case MVE_VMLALDAVaxs32:
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case MVE_VMLALDAVs16:
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case MVE_VMLALDAVs32:
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case MVE_VMLALDAVu16:
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case MVE_VMLALDAVu32:
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case MVE_VMLALDAVxs16:
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case MVE_VMLALDAVxs32:
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case MVE_VMLSDAVas16:
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case MVE_VMLSDAVas32:
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case MVE_VMLSDAVas8:
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case MVE_VMLSDAVaxs16:
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case MVE_VMLSDAVaxs32:
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case MVE_VMLSDAVaxs8:
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case MVE_VMLSDAVs16:
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case MVE_VMLSDAVs32:
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case MVE_VMLSDAVs8:
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case MVE_VMLSDAVxs16:
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case MVE_VMLSDAVxs32:
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case MVE_VMLSDAVxs8:
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case MVE_VMLSLDAVas16:
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case MVE_VMLSLDAVas32:
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case MVE_VMLSLDAVaxs16:
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case MVE_VMLSLDAVaxs32:
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case MVE_VMLSLDAVs16:
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case MVE_VMLSLDAVs32:
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case MVE_VMLSLDAVxs16:
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case MVE_VMLSLDAVxs32:
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case MVE_VRMLALDAVHas32:
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case MVE_VRMLALDAVHau32:
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case MVE_VRMLALDAVHaxs32:
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case MVE_VRMLALDAVHs32:
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case MVE_VRMLALDAVHu32:
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case MVE_VRMLALDAVHxs32:
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case MVE_VRMLSLDAVHas32:
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case MVE_VRMLSLDAVHaxs32:
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case MVE_VRMLSLDAVHs32:
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case MVE_VRMLSLDAVHxs32:
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return true;
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}
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return false;
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};
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LLVMInitializeARMTargetInfo();
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LLVMInitializeARMTarget();
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LLVMInitializeARMTargetMC();
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auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
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std::string Error;
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const Target *T = TargetRegistry::lookupTarget(TT, Error);
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if (!T) {
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dbgs() << Error;
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return;
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}
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TargetOptions Options;
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auto TM = std::unique_ptr<LLVMTargetMachine>(
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static_cast<LLVMTargetMachine*>(
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T->createTargetMachine(TT, "generic", "", Options, None, None,
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CodeGenOpt::Default)));
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ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()),
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*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
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const ARMBaseInstrInfo *TII = ST.getInstrInfo();
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auto MII = TM->getMCInstrInfo();
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for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
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const MCInstrDesc &Desc = TII->get(i);
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uint64_t Flags = Desc.TSFlags;
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if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
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continue;
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bool Valid = (Flags & ARMII::HorizontalReduction) != 0;
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ASSERT_EQ(HorizontalReduction(i), Valid)
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<< MII->getName(i)
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<< ": mismatched expectation for tail-predicated safety\n";
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}
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}
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TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) {
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using namespace ARM;
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