mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 12:41:49 +01:00
[Hexagon] Tidy up some code, NFC: reapply r277372 with a fix
llvm-svn: 277383
This commit is contained in:
Krzysztof Parzyszek
parent
79800f1511
commit
6f6fbffa9f
@ -78,8 +78,8 @@ public:
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return true;
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}
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virtual void PreprocessISelDAG() override;
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virtual void EmitFunctionEntryCode() override;
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void PreprocessISelDAG() override;
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void EmitFunctionEntryCode() override;
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void Select(SDNode *N) override;
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@ -127,11 +127,9 @@ public:
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// the single bit 32 bit mask represents.
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// Used in Clr and Set bit immediate memops.
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SDValue XformMskToBitPosU5Imm(uint32_t Imm, const SDLoc &DL) {
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int32_t bitPos;
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bitPos = Log2_32(Imm);
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assert(bitPos >= 0 && bitPos < 32 &&
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"Constant out of range for 32 BitPos Memops");
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return CurDAG->getTargetConstant(bitPos, DL, MVT::i32);
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unsigned BitPos = Log2_32(Imm);
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assert(BitPos < 32 && "Constant out of range for 32 BitPos Memops");
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return CurDAG->getTargetConstant(BitPos, DL, MVT::i32);
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}
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// XformMskToBitPosU4Imm - Returns the bit position which the single-bit
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@ -667,7 +665,6 @@ void HexagonDAGToDAGISel::SelectStore(SDNode *N) {
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void HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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SDLoc dl(N);
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//
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// %conv.i = sext i32 %tmp1 to i64
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// %conv2.i = sext i32 %add to i64
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// %mul.i = mul nsw i64 %conv2.i, %conv.i
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@ -692,7 +689,6 @@ void HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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SelectCode(N);
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return;
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}
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OP0 = Sext0;
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} else if (MulOp0.getOpcode() == ISD::LOAD) {
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LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
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@ -702,7 +698,6 @@ void HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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SelectCode(N);
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return;
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}
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SDValue Chain = LD->getChain();
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
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OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
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@ -721,7 +716,6 @@ void HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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SelectCode(N);
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return;
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}
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OP1 = Sext1;
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} else if (MulOp1.getOpcode() == ISD::LOAD) {
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LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
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@ -731,7 +725,6 @@ void HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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SelectCode(N);
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return;
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}
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SDValue Chain = LD->getChain();
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
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OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
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@ -744,8 +737,8 @@ void HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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}
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// Generate a mpy instruction.
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SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
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OP0, OP1);
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SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl,
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MVT::i64, OP0, OP1);
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ReplaceNode(N, Result);
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return;
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}
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@ -755,68 +748,56 @@ void HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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void HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
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SDLoc dl(N);
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if (N->getValueType(0) == MVT::i32) {
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SDValue Shl_0 = N->getOperand(0);
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SDValue Shl_1 = N->getOperand(1);
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auto Default = [this,N] () -> void { SelectCode(N); };
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if (N->getValueType(0) != MVT::i32 || Shl_1.getOpcode() != ISD::Constant)
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return Default();
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// RHS is const.
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if (Shl_1.getOpcode() == ISD::Constant) {
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int32_t ShlConst = cast<ConstantSDNode>(Shl_1)->getSExtValue();
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if (Shl_0.getOpcode() == ISD::MUL) {
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SDValue Mul_0 = Shl_0.getOperand(0); // Val
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SDValue Mul_1 = Shl_0.getOperand(1); // Const
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// RHS of mul is const.
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if (Mul_1.getOpcode() == ISD::Constant) {
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int32_t ShlConst =
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cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
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int32_t MulConst =
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cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
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int32_t ValConst = MulConst << ShlConst;
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SDValue Val = CurDAG->getTargetConstant(ValConst, dl,
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MVT::i32);
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
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if (isInt<9>(CN->getSExtValue())) {
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SDNode* Result =
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CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mul_1)) {
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int32_t ValConst = C->getSExtValue() << ShlConst;
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if (isInt<9>(ValConst)) {
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SDValue Val = CurDAG->getTargetConstant(ValConst, dl, MVT::i32);
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SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
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MVT::i32, Mul_0, Val);
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ReplaceNode(N, Result);
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return;
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}
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}
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} else if (Shl_0.getOpcode() == ISD::SUB) {
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return Default();
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}
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if (Shl_0.getOpcode() == ISD::SUB) {
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SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
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SDValue Sub_1 = Shl_0.getOperand(1); // Val
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if (Sub_0.getOpcode() == ISD::Constant) {
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int32_t SubConst =
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cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
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if (SubConst == 0) {
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if (Sub_1.getOpcode() == ISD::SHL) {
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if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Sub_0)) {
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if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL)
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return Default();
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SDValue Shl2_0 = Sub_1.getOperand(0); // Val
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SDValue Shl2_1 = Sub_1.getOperand(1); // Const
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if (Shl2_1.getOpcode() == ISD::Constant) {
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int32_t ShlConst =
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cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
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int32_t Shl2Const =
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cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
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int32_t ValConst = 1 << (ShlConst+Shl2Const);
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SDValue Val = CurDAG->getTargetConstant(-ValConst, dl,
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MVT::i32);
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if (ConstantSDNode *CN =
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dyn_cast<ConstantSDNode>(Val.getNode()))
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if (isInt<9>(CN->getSExtValue())) {
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SDNode* Result =
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CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
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Shl2_0, Val);
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if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(Shl2_1)) {
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int32_t ValConst = 1 << (ShlConst + C2->getSExtValue());
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if (isInt<9>(-ValConst)) {
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SDValue Val = CurDAG->getTargetConstant(-ValConst, dl, MVT::i32);
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SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
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MVT::i32, Shl2_0, Val);
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ReplaceNode(N, Result);
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return;
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}
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}
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}
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}
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}
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}
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}
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}
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SelectCode(N);
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return Default();
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}
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@ -866,21 +847,18 @@ void HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
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return;
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}
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SDNode *IsIntrinsic = N->getOperand(0).getNode();
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if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
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unsigned ID =
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cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
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SDNode *Int = N->getOperand(0).getNode();
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if ((Int->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
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unsigned ID = cast<ConstantSDNode>(Int->getOperand(0))->getZExtValue();
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if (doesIntrinsicReturnPredicate(ID)) {
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// Now we need to differentiate target data types.
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if (N->getValueType(0) == MVT::i64) {
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// Convert the zero_extend to Rs = Pd followed by A2_combinew(0,Rs).
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
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SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
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MVT::i32,
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SDValue(IsIntrinsic, 0));
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MVT::i32, SDValue(Int, 0));
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SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl,
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MVT::i32,
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TargetConst0);
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MVT::i32, TargetConst0);
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SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
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MVT::i64, MVT::Other,
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SDValue(Result_2, 0),
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@ -891,8 +869,7 @@ void HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
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if (N->getValueType(0) == MVT::i32) {
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// Convert the zero_extend to Rs = Pd
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SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
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MVT::i32,
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SDValue(IsIntrinsic, 0));
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MVT::i32, SDValue(Int, 0));
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ReplaceNode(N, RsPd);
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return;
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}
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@ -956,7 +933,7 @@ void HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
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APF.convertToFloat(), dl, MVT::f32)));
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return;
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}
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else if (N->getValueType(0) == MVT::f64) {
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if (N->getValueType(0) == MVT::f64) {
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ReplaceNode(
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N, CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
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CurDAG->getTargetConstantFP(
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@ -1001,8 +978,8 @@ void HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
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}
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// Identify nodes of the form: add(asr(...)).
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SDNode* Src1 = N->getOperand(0).getNode();
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if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
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|| Src1->getValueType(0) != MVT::i32) {
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if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse() ||
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Src1->getValueType(0) != MVT::i32) {
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SelectCode(N);
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return;
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}
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@ -1173,7 +1150,7 @@ void HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
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SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
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SDLoc DL(N);
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SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
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SDNode *R = 0;
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SDNode *R = nullptr;
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// Use TFR_FI when:
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// - the object is fixed, or
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@ -1768,7 +1745,7 @@ SDValue HexagonDAGToDAGISel::getMultiplierForSHL(SDNode *N) {
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static unsigned getPowerOf2Factor(SDValue Val) {
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if (Val.getOpcode() == ISD::MUL) {
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unsigned MaxFactor = 0;
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for (int i=0; i < 2; ++i) {
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for (int i = 0; i < 2; ++i) {
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(i));
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if (!C)
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continue;
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@ -1791,9 +1768,9 @@ static unsigned getPowerOf2Factor(SDValue Val) {
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static bool willShiftRightEliminate(SDValue V, unsigned Amount) {
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if (V.getOpcode() == ISD::MUL) {
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SDValue Ops[] = { V.getOperand(0), V.getOperand(1) };
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for (int i=0; i < 2; ++i)
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for (int i = 0; i < 2; ++i)
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if (isa<ConstantSDNode>(Ops[i].getNode()) &&
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V.getConstantOperandVal(i) % ((uint64_t)1 << Amount) == 0) {
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V.getConstantOperandVal(i) % (1ULL << Amount) == 0) {
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uint64_t NewConst = V.getConstantOperandVal(i) >> Amount;
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return (NewConst == 1);
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}
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@ -2111,6 +2088,9 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) {
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Leaves.pushToBottom(Leaves.pop());
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}
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const DataLayout &DL = CurDAG->getDataLayout();
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const TargetLowering &TLI = *getTargetLowering();
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// Rebuild the tree using Huffman's algorithm
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while (Leaves.size() > 1) {
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WeightedLeaf L0 = Leaves.pop();
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@ -2156,7 +2136,7 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) {
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ISD::SHL, SDLoc(V0), VT, V0,
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CurDAG->getConstant(
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V1C->getAPIntValue().logBase2(), SDLoc(N),
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getTargetLowering()->getScalarShiftAmountTy(CurDAG->getDataLayout(), V0.getValueType())));
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TLI.getScalarShiftAmountTy(DL, V0.getValueType())));
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else
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NewNode = CurDAG->getNode(NOpcode, SDLoc(N), VT, V0, V1);
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@ -2184,9 +2164,9 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) {
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SDValue V0 = NewRoot.getOperand(0);
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NewRoot = CurDAG->getNode(
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ISD::SHL, SDLoc(NewRoot), VT, V0,
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CurDAG->getConstant(V1C->getAPIntValue().logBase2(), SDLoc(NewRoot),
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getTargetLowering()->getScalarShiftAmountTy(
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CurDAG->getDataLayout(), V0.getValueType())));
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CurDAG->getConstant(
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V1C->getAPIntValue().logBase2(), SDLoc(NewRoot),
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TLI.getScalarShiftAmountTy(DL, V0.getValueType())));
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}
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}
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@ -2209,8 +2189,7 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) {
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}
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void HexagonDAGToDAGISel::rebalanceAddressTrees() {
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for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
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E = CurDAG->allnodes_end(); I != E;) {
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for (auto I = CurDAG->allnodes_begin(), E = CurDAG->allnodes_end(); I != E;) {
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SDNode *N = &*I++;
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if (N->getOpcode() != ISD::LOAD && N->getOpcode() != ISD::STORE)
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continue;
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@ -2274,4 +2253,3 @@ void HexagonDAGToDAGISel::rebalanceAddressTrees() {
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RootWeights.clear();
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}
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@ -105,7 +105,7 @@ namespace {
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// Implement calling convention for Hexagon.
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static bool IsHvxVectorType(MVT ty);
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static bool isHvxVectorType(MVT ty);
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static bool
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CC_Hexagon(unsigned ValNo, MVT ValVT,
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@ -159,13 +159,13 @@ CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
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}
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// Deal with un-named arguments.
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unsigned ofst;
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unsigned Offset;
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if (ArgFlags.isByVal()) {
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// If pass-by-value, the size allocated on stack is decided
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// by ArgFlags.getByValSize(), not by the size of LocVT.
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ofst = State.AllocateStack(ArgFlags.getByValSize(),
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Offset = State.AllocateStack(ArgFlags.getByValSize(),
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ArgFlags.getByValAlign());
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
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return false;
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}
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if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
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@ -179,43 +179,43 @@ CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
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LocInfo = CCValAssign::AExt;
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}
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if (LocVT == MVT::i32 || LocVT == MVT::f32) {
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ofst = State.AllocateStack(4, 4);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
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Offset = State.AllocateStack(4, 4);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
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return false;
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}
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if (LocVT == MVT::i64 || LocVT == MVT::f64) {
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ofst = State.AllocateStack(8, 8);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
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Offset = State.AllocateStack(8, 8);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
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return false;
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}
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if (LocVT == MVT::v2i64 || LocVT == MVT::v4i32 || LocVT == MVT::v8i16 ||
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LocVT == MVT::v16i8) {
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ofst = State.AllocateStack(16, 16);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
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Offset = State.AllocateStack(16, 16);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
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return false;
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}
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if (LocVT == MVT::v4i64 || LocVT == MVT::v8i32 || LocVT == MVT::v16i16 ||
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LocVT == MVT::v32i8) {
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ofst = State.AllocateStack(32, 32);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
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Offset = State.AllocateStack(32, 32);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
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return false;
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}
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if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
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LocVT == MVT::v64i8 || LocVT == MVT::v512i1) {
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ofst = State.AllocateStack(64, 64);
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||||
State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
|
||||
Offset = State.AllocateStack(64, 64);
|
||||
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
|
||||
return false;
|
||||
}
|
||||
if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
|
||||
LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) {
|
||||
ofst = State.AllocateStack(128, 128);
|
||||
State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
|
||||
Offset = State.AllocateStack(128, 128);
|
||||
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
|
||||
return false;
|
||||
}
|
||||
if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
|
||||
LocVT == MVT::v256i8) {
|
||||
ofst = State.AllocateStack(256, 256);
|
||||
State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
|
||||
Offset = State.AllocateStack(256, 256);
|
||||
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -266,7 +266,7 @@ static bool CC_Hexagon (unsigned ValNo, MVT ValVT, MVT LocVT,
|
||||
return false;
|
||||
}
|
||||
|
||||
if (IsHvxVectorType(LocVT)) {
|
||||
if (isHvxVectorType(LocVT)) {
|
||||
if (!CC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
|
||||
return false;
|
||||
}
|
||||
@ -322,18 +322,16 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
|
||||
MVT LocVT, CCValAssign::LocInfo LocInfo,
|
||||
ISD::ArgFlagsTy ArgFlags, CCState &State) {
|
||||
|
||||
static const MCPhysReg VecLstS[] = { Hexagon::V0, Hexagon::V1,
|
||||
Hexagon::V2, Hexagon::V3,
|
||||
Hexagon::V4, Hexagon::V5,
|
||||
Hexagon::V6, Hexagon::V7,
|
||||
Hexagon::V8, Hexagon::V9,
|
||||
Hexagon::V10, Hexagon::V11,
|
||||
Hexagon::V12, Hexagon::V13,
|
||||
Hexagon::V14, Hexagon::V15};
|
||||
static const MCPhysReg VecLstD[] = { Hexagon::W0, Hexagon::W1,
|
||||
Hexagon::W2, Hexagon::W3,
|
||||
Hexagon::W4, Hexagon::W5,
|
||||
Hexagon::W6, Hexagon::W7};
|
||||
static const MCPhysReg VecLstS[] = {
|
||||
Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
|
||||
Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
|
||||
Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
|
||||
Hexagon::V15
|
||||
};
|
||||
static const MCPhysReg VecLstD[] = {
|
||||
Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4,
|
||||
Hexagon::W5, Hexagon::W6, Hexagon::W7
|
||||
};
|
||||
auto &MF = State.getMachineFunction();
|
||||
auto &HST = MF.getSubtarget<HexagonSubtarget>();
|
||||
bool UseHVX = HST.useHVXOps();
|
||||
@ -458,7 +456,7 @@ static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
|
||||
// return structs using these additional registers.
|
||||
static const uint16_t RegList[] = { Hexagon::R0, Hexagon::R1,
|
||||
Hexagon::R2, Hexagon::R3,
|
||||
Hexagon::R4, Hexagon::R5};
|
||||
Hexagon::R4, Hexagon::R5 };
|
||||
if (unsigned Reg = State.AllocateReg(RegList)) {
|
||||
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
|
||||
return false;
|
||||
@ -531,7 +529,7 @@ void HexagonTargetLowering::promoteLdStType(MVT VT, MVT PromotedLdStVT) {
|
||||
|
||||
SDValue
|
||||
HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
|
||||
const {
|
||||
const {
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
@ -543,7 +541,6 @@ const {
|
||||
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
|
||||
SDValue Chain, ISD::ArgFlagsTy Flags,
|
||||
SelectionDAG &DAG, const SDLoc &dl) {
|
||||
|
||||
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
|
||||
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
|
||||
/*isVolatile=*/false, /*AlwaysInline=*/false,
|
||||
@ -551,14 +548,26 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
|
||||
MachinePointerInfo(), MachinePointerInfo());
|
||||
}
|
||||
|
||||
static bool IsHvxVectorType(MVT ty) {
|
||||
return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 ||
|
||||
ty == MVT::v64i8 ||
|
||||
ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 ||
|
||||
ty == MVT::v128i8 ||
|
||||
ty == MVT::v32i64 || ty == MVT::v64i32 || ty == MVT::v128i16 ||
|
||||
ty == MVT::v256i8 ||
|
||||
ty == MVT::v512i1 || ty == MVT::v1024i1);
|
||||
static bool isHvxVectorType(MVT Ty) {
|
||||
switch (Ty.SimpleTy) {
|
||||
case MVT::v8i64:
|
||||
case MVT::v16i32:
|
||||
case MVT::v32i16:
|
||||
case MVT::v64i8:
|
||||
case MVT::v16i64:
|
||||
case MVT::v32i32:
|
||||
case MVT::v64i16:
|
||||
case MVT::v128i8:
|
||||
case MVT::v32i64:
|
||||
case MVT::v64i32:
|
||||
case MVT::v128i16:
|
||||
case MVT::v256i8:
|
||||
case MVT::v512i1:
|
||||
case MVT::v1024i1:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
// LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
|
||||
@ -675,17 +684,17 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
|
||||
SDValue Chain = CLI.Chain;
|
||||
SDValue Callee = CLI.Callee;
|
||||
bool &isTailCall = CLI.IsTailCall;
|
||||
bool &IsTailCall = CLI.IsTailCall;
|
||||
CallingConv::ID CallConv = CLI.CallConv;
|
||||
bool isVarArg = CLI.IsVarArg;
|
||||
bool doesNotReturn = CLI.DoesNotReturn;
|
||||
bool IsVarArg = CLI.IsVarArg;
|
||||
bool DoesNotReturn = CLI.DoesNotReturn;
|
||||
|
||||
bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
|
||||
MachineFunction &MF = DAG.getMachineFunction();
|
||||
auto PtrVT = getPointerTy(MF.getDataLayout());
|
||||
|
||||
// Check for varargs.
|
||||
int NumNamedVarArgParams = -1;
|
||||
unsigned NumNamedVarArgParams = -1U;
|
||||
if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee)) {
|
||||
const GlobalValue *GV = GAN->getGlobal();
|
||||
Callee = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
|
||||
@ -700,32 +709,32 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
|
||||
// Analyze operands of the call, assigning locations to each operand.
|
||||
SmallVector<CCValAssign, 16> ArgLocs;
|
||||
HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
|
||||
HexagonCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
|
||||
*DAG.getContext(), NumNamedVarArgParams);
|
||||
|
||||
if (isVarArg)
|
||||
if (IsVarArg)
|
||||
CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
|
||||
else
|
||||
CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
|
||||
|
||||
auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
|
||||
if (Attr.getValueAsString() == "true")
|
||||
isTailCall = false;
|
||||
IsTailCall = false;
|
||||
|
||||
if (isTailCall) {
|
||||
if (IsTailCall) {
|
||||
bool StructAttrFlag = MF.getFunction()->hasStructRetAttr();
|
||||
isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
|
||||
isVarArg, IsStructRet,
|
||||
IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
|
||||
IsVarArg, IsStructRet,
|
||||
StructAttrFlag,
|
||||
Outs, OutVals, Ins, DAG);
|
||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||
CCValAssign &VA = ArgLocs[i];
|
||||
if (VA.isMemLoc()) {
|
||||
isTailCall = false;
|
||||
IsTailCall = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
DEBUG(dbgs() << (isTailCall ? "Eligible for Tail Call\n"
|
||||
DEBUG(dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
|
||||
: "Argument must be passed on stack. "
|
||||
"Not eligible for Tail Call\n"));
|
||||
}
|
||||
@ -746,7 +755,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
SDValue Arg = OutVals[i];
|
||||
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
||||
// Record if we need > 8 byte alignment on an argument.
|
||||
bool ArgAlign = IsHvxVectorType(VA.getValVT());
|
||||
bool ArgAlign = isHvxVectorType(VA.getValVT());
|
||||
NeedsArgAlign |= ArgAlign;
|
||||
|
||||
// Promote the value if needed.
|
||||
@ -812,21 +821,21 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
if (!MemOpChains.empty())
|
||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||
|
||||
if (!isTailCall) {
|
||||
if (!IsTailCall) {
|
||||
SDValue C = DAG.getConstant(NumBytes, dl, PtrVT, true);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, C, dl);
|
||||
}
|
||||
|
||||
// Build a sequence of copy-to-reg nodes chained together with token
|
||||
// chain and flag operands which copy the outgoing args into registers.
|
||||
// The InFlag in necessary since all emitted instructions must be
|
||||
// The Glue is necessary since all emitted instructions must be
|
||||
// stuck together.
|
||||
SDValue InFlag;
|
||||
if (!isTailCall) {
|
||||
SDValue Glue;
|
||||
if (!IsTailCall) {
|
||||
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
||||
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
|
||||
RegsToPass[i].second, InFlag);
|
||||
InFlag = Chain.getValue(1);
|
||||
RegsToPass[i].second, Glue);
|
||||
Glue = Chain.getValue(1);
|
||||
}
|
||||
} else {
|
||||
// For tail calls lower the arguments to the 'real' stack slot.
|
||||
@ -839,13 +848,13 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
// on every argument instead of just those arguments it would clobber.
|
||||
//
|
||||
// Do not flag preceding copytoreg stuff together with the following stuff.
|
||||
InFlag = SDValue();
|
||||
Glue = SDValue();
|
||||
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
||||
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
|
||||
RegsToPass[i].second, InFlag);
|
||||
InFlag = Chain.getValue(1);
|
||||
RegsToPass[i].second, Glue);
|
||||
Glue = Chain.getValue(1);
|
||||
}
|
||||
InFlag = SDValue();
|
||||
Glue = SDValue();
|
||||
}
|
||||
|
||||
bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
|
||||
@ -874,33 +883,32 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
RegsToPass[i].second.getValueType()));
|
||||
}
|
||||
|
||||
if (InFlag.getNode())
|
||||
Ops.push_back(InFlag);
|
||||
if (Glue.getNode())
|
||||
Ops.push_back(Glue);
|
||||
|
||||
if (isTailCall) {
|
||||
if (IsTailCall) {
|
||||
MF.getFrameInfo().setHasTailCall();
|
||||
return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
|
||||
}
|
||||
|
||||
int OpCode = doesNotReturn ? HexagonISD::CALLv3nr : HexagonISD::CALLv3;
|
||||
unsigned OpCode = DoesNotReturn ? HexagonISD::CALLv3nr : HexagonISD::CALLv3;
|
||||
Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
|
||||
InFlag = Chain.getValue(1);
|
||||
Glue = Chain.getValue(1);
|
||||
|
||||
// Create the CALLSEQ_END node.
|
||||
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
|
||||
DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
|
||||
InFlag = Chain.getValue(1);
|
||||
DAG.getIntPtrConstant(0, dl, true), Glue, dl);
|
||||
Glue = Chain.getValue(1);
|
||||
|
||||
// Handle result values, copying them out of physregs into vregs that we
|
||||
// return.
|
||||
return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
|
||||
return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
|
||||
InVals, OutVals, Callee);
|
||||
}
|
||||
|
||||
static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
|
||||
bool isSEXTLoad, SDValue &Base,
|
||||
SDValue &Offset, bool &isInc,
|
||||
SelectionDAG &DAG) {
|
||||
SDValue &Base, SDValue &Offset,
|
||||
bool &IsInc, SelectionDAG &DAG) {
|
||||
if (Ptr->getOpcode() != ISD::ADD)
|
||||
return false;
|
||||
|
||||
@ -917,11 +925,11 @@ static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
|
||||
|
||||
if (ValidHVXDblType || ValidHVXType ||
|
||||
VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
|
||||
isInc = (Ptr->getOpcode() == ISD::ADD);
|
||||
IsInc = (Ptr->getOpcode() == ISD::ADD);
|
||||
Base = Ptr->getOperand(0);
|
||||
Offset = Ptr->getOperand(1);
|
||||
// Ensure that Offset is a constant.
|
||||
return (isa<ConstantSDNode>(Offset));
|
||||
return isa<ConstantSDNode>(Offset);
|
||||
}
|
||||
|
||||
return false;
|
||||
@ -938,28 +946,24 @@ bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
|
||||
{
|
||||
EVT VT;
|
||||
SDValue Ptr;
|
||||
bool isSEXTLoad = false;
|
||||
|
||||
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
|
||||
VT = LD->getMemoryVT();
|
||||
isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
|
||||
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
||||
VT = ST->getMemoryVT();
|
||||
if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
|
||||
if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore())
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
|
||||
bool isInc = false;
|
||||
bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
|
||||
isInc, DAG);
|
||||
bool IsInc = false;
|
||||
bool isLegal = getIndexedAddressParts(Op, VT, Base, Offset, IsInc, DAG);
|
||||
if (isLegal) {
|
||||
auto &HII = *Subtarget.getInstrInfo();
|
||||
int32_t OffsetVal = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
|
||||
if (HII.isValidAutoIncImm(VT, OffsetVal)) {
|
||||
AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
|
||||
AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@ -2283,7 +2287,6 @@ bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
|
||||
bool
|
||||
HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
|
||||
unsigned DefinedValues) const {
|
||||
|
||||
// Hexagon vector shuffle operates on element sizes of bytes or halfwords
|
||||
EVT EltVT = VT.getVectorElementType();
|
||||
int EltBits = EltVT.getSizeInBits();
|
||||
@ -2346,11 +2349,12 @@ HexagonTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
|
||||
if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
|
||||
!isa<ConstantSDNode>(V1.getOperand(0))) {
|
||||
bool IsScalarToVector = true;
|
||||
for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
|
||||
for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i) {
|
||||
if (!V1.getOperand(i).isUndef()) {
|
||||
IsScalarToVector = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (IsScalarToVector)
|
||||
return createSplat(DAG, dl, VT, V1.getOperand(0));
|
||||
}
|
||||
@ -2716,7 +2720,7 @@ HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
|
||||
// If we are dealing with EXTRACT_SUBVECTOR on a HVX type, we may
|
||||
// be able to simplify it to an EXTRACT_SUBREG.
|
||||
if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR && Subtarget.useHVXOps() &&
|
||||
IsHvxVectorType(Op.getValueType().getSimpleVT()))
|
||||
isHvxVectorType(Op.getValueType().getSimpleVT()))
|
||||
return LowerEXTRACT_SUBVECTOR_HVX(Op, DAG);
|
||||
|
||||
EVT VT = Op.getValueType();
|
||||
@ -3060,7 +3064,8 @@ bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL,
|
||||
return false;
|
||||
|
||||
int Scale = AM.Scale;
|
||||
if (Scale < 0) Scale = -Scale;
|
||||
if (Scale < 0)
|
||||
Scale = -Scale;
|
||||
switch (Scale) {
|
||||
case 0: // No scale reg, "r+i", "r", or just "i".
|
||||
break;
|
||||
@ -3109,8 +3114,8 @@ bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
|
||||
// ***************************************************************************
|
||||
|
||||
// If this is a tail call via a function pointer, then don't do it!
|
||||
if (!(isa<GlobalAddressSDNode>(Callee)) &&
|
||||
!(isa<ExternalSymbolSDNode>(Callee))) {
|
||||
if (!isa<GlobalAddressSDNode>(Callee) &&
|
||||
!isa<ExternalSymbolSDNode>(Callee)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user