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Relocation enablement for PPC DAG postprocessing pass
llvm-svn: 175693
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@ -151,8 +151,22 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
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Type = ELF::R_PPC64_TOC;
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break;
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case PPC::fixup_ppc_toc16:
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switch (Modifier) {
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default: llvm_unreachable("Unsupported Modifier");
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case MCSymbolRefExpr::VK_PPC_DTPREL16_LO:
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Type = ELF::R_PPC64_DTPREL16_LO;
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break;
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case MCSymbolRefExpr::VK_None:
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Type = ELF::R_PPC64_TOC16;
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break;
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case MCSymbolRefExpr::VK_PPC_TOC16_LO:
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Type = ELF::R_PPC64_TOC16_LO;
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break;
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case MCSymbolRefExpr::VK_PPC_GOT_TLSLD16_LO:
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Type = ELF::R_PPC64_GOT_TLSLD16_LO;
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break;
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}
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break;
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case PPC::fixup_ppc_toc16_ds:
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switch (Modifier) {
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default: llvm_unreachable("Unsupported Modifier");
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@ -57,26 +57,32 @@ namespace llvm {
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/// MO_PIC_FLAG - If this bit is set, the symbol reference is relative to
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/// the function's picbase, e.g. lo16(symbol-picbase).
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MO_PIC_FLAG = 4,
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MO_PIC_FLAG = 2,
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/// MO_NLP_FLAG - If this bit is set, the symbol reference is actually to
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/// the non_lazy_ptr for the global, e.g. lo16(symbol$non_lazy_ptr-picbase).
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MO_NLP_FLAG = 8,
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MO_NLP_FLAG = 4,
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/// MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a
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/// symbol with hidden visibility. This causes a different kind of
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/// non-lazy-pointer to be generated.
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MO_NLP_HIDDEN_FLAG = 16,
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MO_NLP_HIDDEN_FLAG = 8,
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/// The next are not flags but distinct values.
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MO_ACCESS_MASK = 0xe0,
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MO_ACCESS_MASK = 0xf0,
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/// MO_LO16, MO_HA16 - lo16(symbol) and ha16(symbol)
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MO_LO16 = 1 << 5,
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MO_HA16 = 2 << 5,
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MO_LO16 = 1 << 4,
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MO_HA16 = 2 << 4,
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MO_TPREL16_HA = 3 << 5,
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MO_TPREL16_LO = 4 << 5
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MO_TPREL16_HA = 3 << 4,
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MO_TPREL16_LO = 4 << 4,
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/// These values identify relocations on immediates folded
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/// into memory operations.
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MO_DTPREL16_LO = 5 << 4,
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MO_TLSLD16_LO = 6 << 4,
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MO_TOC16_LO = 7 << 4
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};
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} // end namespace PPCII
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@ -346,7 +346,7 @@ def crbitm: Operand<i8> {
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// Address operands
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def memri : Operand<iPTR> {
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let PrintMethod = "printMemRegImm";
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let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
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let MIOperandInfo = (ops symbolLo:$imm, ptr_rc:$reg);
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let EncoderMethod = "getMemRIEncoding";
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}
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def memrr : Operand<iPTR> {
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@ -355,7 +355,7 @@ def memrr : Operand<iPTR> {
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}
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def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
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let PrintMethod = "printMemRegImmShifted";
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let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
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let MIOperandInfo = (ops symbolLo:$imm, ptr_rc:$reg);
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let EncoderMethod = "getMemRIXEncoding";
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}
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@ -115,6 +115,12 @@ static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
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break;
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case PPCII::MO_TPREL16_LO: RefKind = MCSymbolRefExpr::VK_PPC_TPREL16_LO;
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break;
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case PPCII::MO_DTPREL16_LO: RefKind = MCSymbolRefExpr::VK_PPC_DTPREL16_LO;
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break;
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case PPCII::MO_TLSLD16_LO: RefKind = MCSymbolRefExpr::VK_PPC_GOT_TLSLD16_LO;
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break;
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case PPCII::MO_TOC16_LO: RefKind = MCSymbolRefExpr::VK_PPC_TOC16_LO;
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break;
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}
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// FIXME: This isn't right, but we don't have a good way to express this in
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