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Fix an assert in SelectionDAGBuilder when processing inline asm

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When processing inline asm that contains errors, make sure we can recover
gracefully by creating an UNDEF SDValue for the inline asm statement before
returning from SelectionDAGBuilder::visitInlineAsm. This is necessary for
consumers that don't exit on the first error that is emitted (e.g. clang)
and that would assert later on.

Fixes PR24071.

Patch by Diana Picus.

llvm-svn: 269811
This commit is contained in:
Renato Golin 2016-05-17 19:52:01 +00:00
parent 6f0b608b03
commit 6fa4110be7
11 changed files with 39 additions and 34 deletions
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53
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -6798,10 +6798,9 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
// Copy the output from the appropriate register. Find a register that
// we can use.
if (OpInfo.AssignedRegs.Regs.empty()) {
LLVMContext &Ctx = *DAG.getContext();
Ctx.emitError(CS.getInstruction(),
"couldn't allocate output register for constraint '" +
Twine(OpInfo.ConstraintCode) + "'");
emitInlineAsmError(
CS, "couldn't allocate output register for constraint '" +
Twine(OpInfo.ConstraintCode) + "'");
return;
}
@ -6854,10 +6853,9 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
// Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
if (OpInfo.isIndirect) {
// This happens on gcc/testsuite/gcc.dg/pr8788-1.c
LLVMContext &Ctx = *DAG.getContext();
Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
" don't know how to handle tied "
"indirect register inputs");
emitInlineAsmError(CS, "inline asm not supported yet:"
" don't know how to handle tied "
"indirect register inputs");
return;
}
@ -6871,10 +6869,9 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
else {
LLVMContext &Ctx = *DAG.getContext();
Ctx.emitError(CS.getInstruction(),
"inline asm error: This value"
" type register class is not natively supported!");
emitInlineAsmError(
CS, "inline asm error: This value"
" type register class is not natively supported!");
return;
}
}
@ -6912,10 +6909,8 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
Ops, DAG);
if (Ops.empty()) {
LLVMContext &Ctx = *DAG.getContext();
Ctx.emitError(CS.getInstruction(),
"invalid operand for inline asm constraint '" +
Twine(OpInfo.ConstraintCode) + "'");
emitInlineAsmError(CS, "invalid operand for inline asm constraint '" +
Twine(OpInfo.ConstraintCode) + "'");
return;
}
@ -6955,20 +6950,17 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
// TODO: Support this.
if (OpInfo.isIndirect) {
LLVMContext &Ctx = *DAG.getContext();
Ctx.emitError(CS.getInstruction(),
"Don't know how to handle indirect register inputs yet "
"for constraint '" +
Twine(OpInfo.ConstraintCode) + "'");
emitInlineAsmError(
CS, "Don't know how to handle indirect register inputs yet "
"for constraint '" +
Twine(OpInfo.ConstraintCode) + "'");
return;
}
// Copy the input into the appropriate registers.
if (OpInfo.AssignedRegs.Regs.empty()) {
LLVMContext &Ctx = *DAG.getContext();
Ctx.emitError(CS.getInstruction(),
"couldn't allocate input reg for constraint '" +
Twine(OpInfo.ConstraintCode) + "'");
emitInlineAsmError(CS, "couldn't allocate input reg for constraint '" +
Twine(OpInfo.ConstraintCode) + "'");
return;
}
@ -7066,6 +7058,17 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
DAG.setRoot(Chain);
}
void SelectionDAGBuilder::emitInlineAsmError(ImmutableCallSite CS,
const Twine &Message) {
LLVMContext &Ctx = *DAG.getContext();
Ctx.emitError(CS.getInstruction(), Message);
// Make sure we leave the DAG in a valid state
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
auto VT = TLI.getValueType(DAG.getDataLayout(), CS.getType());
setValue(CS.getInstruction(), DAG.getUNDEF(VT));
}
void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
MVT::Other, getRoot(),

2
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
View File

@ -910,6 +910,8 @@ private:
void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
void emitInlineAsmError(ImmutableCallSite CS, const Twine &Message);
/// EmitFuncArgumentDbgValue - If V is an function argument then create
/// corresponding DBG_VALUE machine instruction for it now. At the end of
/// instruction selection, they will be inserted to the entry BB.

2
test/CodeGen/AArch64/arm64-inline-asm-error-I.ll
View File

@ -1,4 +1,4 @@
; RUN: not llc -march=arm64 -exit-on-error < %s 2> %t
; RUN: not llc -march=arm64 < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant.

2
test/CodeGen/AArch64/arm64-inline-asm-error-J.ll
View File

@ -1,4 +1,4 @@
; RUN: not llc -march=arm64 -exit-on-error < %s 2> %t
; RUN: not llc -march=arm64 < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant.

2
test/CodeGen/AArch64/arm64-inline-asm-error-K.ll
View File

@ -1,4 +1,4 @@
; RUN: not llc -march=arm64 -exit-on-error < %s 2> %t
; RUN: not llc -march=arm64 < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant.

2
test/CodeGen/AArch64/arm64-inline-asm-error-L.ll
View File

@ -1,4 +1,4 @@
; RUN: not llc -march=arm64 -exit-on-error < %s 2> %t
; RUN: not llc -march=arm64 < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant.

2
test/CodeGen/AArch64/arm64-inline-asm-error-M.ll
View File

@ -1,4 +1,4 @@
; RUN: not llc -march=arm64 -exit-on-error < %s 2> %t
; RUN: not llc -march=arm64 < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant.

2
test/CodeGen/AArch64/arm64-inline-asm-error-N.ll
View File

@ -1,4 +1,4 @@
; RUN: not llc -march=arm64 -exit-on-error < %s 2> %t
; RUN: not llc -march=arm64 < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant.

2
test/CodeGen/PowerPC/crbit-asm-disabled.ll
View File

@ -1,4 +1,4 @@
; RUN: not llc -mcpu=pwr7 -exit-on-error -o /dev/null %s 2>&1 | FileCheck %s
; RUN: not llc -mcpu=pwr7 -o /dev/null %s 2>&1 | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"

2
test/CodeGen/PowerPC/vec-asm-disabled.ll
View File

@ -1,4 +1,4 @@
; RUN: not llc -mcpu=pwr7 -exit-on-error -o /dev/null %s 2>&1 | FileCheck %s
; RUN: not llc -mcpu=pwr7 -o /dev/null %s 2>&1 | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"

2
test/CodeGen/X86/asm-reject-reg-type-mismatch.ll
View File

@ -1,4 +1,4 @@
; RUN: not llc -exit-on-error -o /dev/null %s 2>&1 | FileCheck %s
; RUN: not llc -o /dev/null %s 2>&1 | FileCheck %s
target triple = "x86_64--"
; CHECK: error: couldn't allocate output register for constraint '{ax}'