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AMDGPU/GlobalISel: Fix select for v2s16 and/or/xor
llvm-svn: 373180
This commit is contained in:
Matt Arsenault
parent
a384a36087
commit
6fa899ef23
@ -777,6 +777,23 @@ class ZExt_i16_i1_Pat <SDNode ext> : GCNPat <
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$src)
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>;
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foreach vt = [i16, v2i16] in {
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def : GCNPat <
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(and vt:$src0, vt:$src1),
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(V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
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>;
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def : GCNPat <
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(or vt:$src0, vt:$src1),
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(V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
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>;
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def : GCNPat <
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(xor vt:$src0, vt:$src1),
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(V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
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>;
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}
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let Predicates = [Has16BitInsts] in {
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let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
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@ -799,21 +816,6 @@ defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e64, 1>;
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defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e64, 1>;
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}
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def : GCNPat <
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(and i16:$src0, i16:$src1),
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(V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
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>;
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def : GCNPat <
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(or i16:$src0, i16:$src1),
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(V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
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>;
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def : GCNPat <
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(xor i16:$src0, i16:$src1),
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(V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
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>;
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let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
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defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e64>;
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defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e64>;
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@ -1,5 +1,6 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
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---
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@ -148,12 +149,10 @@ body: |
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: and_s16_vgpr_vgpr_vgpr
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; WAVE64: liveins: $vgpr0, $vgpr1
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; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
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; WAVE64: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
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; WAVE64: [[AND:%[0-9]+]]:vgpr(s16) = G_AND [[TRUNC]], [[TRUNC1]]
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; WAVE64: S_ENDPGM 0, implicit [[AND]](s16)
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
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; WAVE32-LABEL: name: and_s16_vgpr_vgpr_vgpr
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; WAVE32: liveins: $vgpr0, $vgpr1
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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@ -355,16 +354,17 @@ body: |
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: and_v2s16_vgpr_vgpr_vgpr
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; WAVE64: liveins: $vgpr0, $vgpr1
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; WAVE64: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
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; WAVE64: [[AND:%[0-9]+]]:vgpr(<2 x s16>) = G_AND [[COPY]], [[COPY1]]
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; WAVE64: S_ENDPGM 0, implicit [[AND]](<2 x s16>)
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
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; WAVE32-LABEL: name: and_v2s16_vgpr_vgpr_vgpr
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; WAVE32: liveins: $vgpr0, $vgpr1
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; WAVE32: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
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; WAVE32: [[AND:%[0-9]+]]:vgpr(<2 x s16>) = G_AND [[COPY]], [[COPY1]]
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; WAVE32: S_ENDPGM 0, implicit [[AND]](<2 x s16>)
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:vgpr(<2 x s16>) = COPY $vgpr1
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%2:vgpr(<2 x s16>) = G_AND %0, %1
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@ -1,5 +1,6 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
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---
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@ -148,12 +149,10 @@ body: |
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: or_s16_vgpr_vgpr_vgpr
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; WAVE64: liveins: $vgpr0, $vgpr1
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; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
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; WAVE64: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
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; WAVE64: [[OR:%[0-9]+]]:vgpr(s16) = G_OR [[TRUNC]], [[TRUNC1]]
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; WAVE64: S_ENDPGM 0, implicit [[OR]](s16)
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
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; WAVE32-LABEL: name: or_s16_vgpr_vgpr_vgpr
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; WAVE32: liveins: $vgpr0, $vgpr1
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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@ -355,16 +354,17 @@ body: |
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: or_v2s16_vgpr_vgpr_vgpr
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; WAVE64: liveins: $vgpr0, $vgpr1
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; WAVE64: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
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; WAVE64: [[OR:%[0-9]+]]:vgpr(<2 x s16>) = G_OR [[COPY]], [[COPY1]]
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; WAVE64: S_ENDPGM 0, implicit [[OR]](<2 x s16>)
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
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; WAVE32-LABEL: name: or_v2s16_vgpr_vgpr_vgpr
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; WAVE32: liveins: $vgpr0, $vgpr1
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; WAVE32: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
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; WAVE32: [[OR:%[0-9]+]]:vgpr(<2 x s16>) = G_OR [[COPY]], [[COPY1]]
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; WAVE32: S_ENDPGM 0, implicit [[OR]](<2 x s16>)
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:vgpr(<2 x s16>) = COPY $vgpr1
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%2:vgpr(<2 x s16>) = G_OR %0, %1
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@ -1,5 +1,6 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
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---
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@ -148,12 +149,10 @@ body: |
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: xor_s16_vgpr_vgpr_vgpr
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; WAVE64: liveins: $vgpr0, $vgpr1
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; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
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; WAVE64: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
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; WAVE64: [[XOR:%[0-9]+]]:vgpr(s16) = G_XOR [[TRUNC]], [[TRUNC1]]
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; WAVE64: S_ENDPGM 0, implicit [[XOR]](s16)
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
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; WAVE32-LABEL: name: xor_s16_vgpr_vgpr_vgpr
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; WAVE32: liveins: $vgpr0, $vgpr1
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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@ -355,16 +354,17 @@ body: |
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: xor_v2s16_vgpr_vgpr_vgpr
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; WAVE64: liveins: $vgpr0, $vgpr1
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; WAVE64: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
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; WAVE64: [[XOR:%[0-9]+]]:vgpr(<2 x s16>) = G_XOR [[COPY]], [[COPY1]]
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; WAVE64: S_ENDPGM 0, implicit [[XOR]](<2 x s16>)
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
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; WAVE32-LABEL: name: xor_v2s16_vgpr_vgpr_vgpr
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; WAVE32: liveins: $vgpr0, $vgpr1
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; WAVE32: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
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; WAVE32: [[XOR:%[0-9]+]]:vgpr(<2 x s16>) = G_XOR [[COPY]], [[COPY1]]
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; WAVE32: S_ENDPGM 0, implicit [[XOR]](<2 x s16>)
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:vgpr(<2 x s16>) = COPY $vgpr1
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%2:vgpr(<2 x s16>) = G_XOR %0, %1
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