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[SVE][CodeGen] Fix implicit TypeSize->uint64_t casts in TypePromotion
The TypePromotion pass only operates on scalar types so I've fixed up all places where we were relying upon the implicit cast from TypeSize->uint64_t. Differential Revision: https://reviews.llvm.org/D88575
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@ -134,8 +134,9 @@ public:
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Ctx(C), OrigTy(Ty), PromotedWidth(Width), Visited(visited),
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Sources(sources), Sinks(sinks), SafeWrap(wrap) {
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ExtTy = IntegerType::get(Ctx, PromotedWidth);
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assert(OrigTy->getPrimitiveSizeInBits() < ExtTy->getPrimitiveSizeInBits()
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&& "Original type not smaller than extended type");
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assert(OrigTy->getPrimitiveSizeInBits().getFixedSize() <
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ExtTy->getPrimitiveSizeInBits().getFixedSize() &&
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"Original type not smaller than extended type");
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}
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void Mutate();
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@ -809,7 +810,7 @@ bool TypePromotion::isLegalToPromote(Value *V) {
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bool TypePromotion::TryToPromote(Value *V, unsigned PromotedWidth) {
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Type *OrigTy = V->getType();
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TypeSize = OrigTy->getPrimitiveSizeInBits();
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TypeSize = OrigTy->getPrimitiveSizeInBits().getFixedSize();
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SafeToPromote.clear();
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SafeWrap.clear();
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@ -980,15 +981,14 @@ bool TypePromotion::runOnFunction(Function &F) {
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if (TLI->getTypeAction(ICmp->getContext(), SrcVT) !=
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TargetLowering::TypePromoteInteger)
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break;
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EVT PromotedVT = TLI->getTypeToTransformTo(ICmp->getContext(), SrcVT);
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if (RegisterBitWidth < PromotedVT.getSizeInBits()) {
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if (RegisterBitWidth < PromotedVT.getFixedSizeInBits()) {
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LLVM_DEBUG(dbgs() << "IR Promotion: Couldn't find target register "
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<< "for promoted type\n");
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break;
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}
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MadeChange |= TryToPromote(I, PromotedVT.getSizeInBits());
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MadeChange |= TryToPromote(I, PromotedVT.getFixedSizeInBits());
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break;
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}
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}
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