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Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph

Browse Source 
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.

llvm-svn: 62275
This commit is contained in:
Dan Gohman 2009-01-15 19:20:50 +00:00
parent db7a9e291a
commit 6fcee67989
28 changed files with 144 additions and 155 deletions
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10
include/llvm/CodeGen/LinkAllCodegenComponents.h
View File

@ -42,11 +42,11 @@ namespace {
llvm::linkOcamlGC();
llvm::linkShadowStackGC();
(void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL, NULL, false);
(void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL, NULL, false);
(void) llvm::createTDListDAGScheduler(NULL, NULL, NULL, NULL, false);
(void) llvm::createFastDAGScheduler(NULL, NULL, NULL, NULL, false);
(void) llvm::createDefaultScheduler(NULL, NULL, NULL, NULL, false);
(void) llvm::createBURRListDAGScheduler(NULL, false);
(void) llvm::createTDRRListDAGScheduler(NULL, false);
(void) llvm::createTDListDAGScheduler(NULL, false);
(void) llvm::createFastDAGScheduler(NULL, false);
(void) llvm::createDefaultScheduler(NULL, false);
}
} ForceCodegenLinking; // Force link by creating a global definition.

7
include/llvm/CodeGen/ScheduleDAG.h
View File

@ -421,15 +421,14 @@ namespace llvm {
const TargetInstrInfo *TII; // Target instruction information
const TargetRegisterInfo *TRI; // Target processor register info
TargetLowering *TLI; // Target lowering info
MachineFunction *MF; // Machine function
MachineFunction &MF; // Machine function
MachineRegisterInfo &MRI; // Virtual/real register map
MachineConstantPool *ConstPool; // Target constant pool
std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
// represent noop instructions.
std::vector<SUnit> SUnits; // The scheduling units.
ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm);
explicit ScheduleDAG(MachineFunction &mf);
virtual ~ScheduleDAG();
@ -440,7 +439,7 @@ namespace llvm {
/// Run - perform scheduling.
///
void Run();
void Run(SelectionDAG *DAG, MachineBasicBlock *MBB);
/// BuildSchedGraph - Build SUnits and set up their Preds and Succs
/// to form the scheduling dependency graph.

20
include/llvm/CodeGen/ScheduleDAGInstrs.h
View File

@ -16,6 +16,7 @@
#define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Target/TargetRegisterInfo.h"
namespace llvm {
class MachineLoopInfo;
@ -25,11 +26,22 @@ namespace llvm {
const MachineLoopInfo &MLI;
const MachineDominatorTree &MDT;
/// Defs, Uses - Remember where defs and uses of each physical register
/// are as we iterate upward through the instructions. This is allocated
/// here instead of inside BuildSchedGraph to avoid the need for it to be
/// initialized and destructed for each block.
std::vector<SUnit *> Defs[TargetRegisterInfo::FirstVirtualRegister];
std::vector<SUnit *> Uses[TargetRegisterInfo::FirstVirtualRegister];
/// PendingLoads - Remember where unknown loads are after the most recent
/// unknown store, as we iterate. As with Defs and Uses, this is here
/// to minimize construction/destruction.
std::vector<SUnit *> PendingLoads;
public:
ScheduleDAGInstrs(MachineBasicBlock *bb,
const TargetMachine &tm,
const MachineLoopInfo &mli,
const MachineDominatorTree &mdt);
explicit ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo &mli,
const MachineDominatorTree &mdt);
virtual ~ScheduleDAGInstrs() {}

3
include/llvm/CodeGen/ScheduleDAGSDNodes.h
View File

@ -74,8 +74,7 @@ namespace llvm {
///
class ScheduleDAGSDNodes : public ScheduleDAG {
public:
ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm);
explicit ScheduleDAGSDNodes(MachineFunction &mf);
virtual ~ScheduleDAGSDNodes() {}

22
include/llvm/CodeGen/SchedulerRegistry.h
View File

@ -32,9 +32,7 @@ class MachineBasicBlock;
class RegisterScheduler : public MachinePassRegistryNode {
public:
typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, SelectionDAG*,
const TargetMachine *,
MachineBasicBlock*, bool);
typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, bool);
static MachinePassRegistry Registry;
@ -66,44 +64,28 @@ public:
/// createBURRListDAGScheduler - This creates a bottom up register usage
/// reduction list scheduler.
ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
/// createTDRRListDAGScheduler - This creates a top down register usage
/// reduction list scheduler.
ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
/// createTDListDAGScheduler - This creates a top-down list scheduler with
/// a hazard recognizer.
ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
/// createFastDAGScheduler - This creates a "fast" scheduler.
///
ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
} // end namespace llvm
#endif

6
include/llvm/CodeGen/SelectionDAGISel.h
View File

@ -41,9 +41,11 @@ namespace llvm {
/// pattern-matching instruction selectors.
class SelectionDAGISel : public FunctionPass {
public:
const TargetMachine &TM;
TargetLowering &TLI;
MachineRegisterInfo *RegInfo;
FunctionLoweringInfo *FuncInfo;
MachineFunction *MF;
MachineRegisterInfo *RegInfo;
SelectionDAG *CurDAG;
SelectionDAGLowering *SDL;
MachineBasicBlock *BB;
@ -52,7 +54,7 @@ public:
bool Fast;
static char ID;
explicit SelectionDAGISel(TargetLowering &tli, bool fast = false);
explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
virtual ~SelectionDAGISel();
TargetLowering &getTargetLowering() { return TLI; }

25
lib/CodeGen/PostRASchedulerList.cpp
View File

@ -27,6 +27,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/Compiler.h"
@ -78,11 +79,17 @@ namespace {
/// Topo - A topological ordering for SUnits.
ScheduleDAGTopologicalSort Topo;
/// AllocatableSet - The set of allocatable registers.
/// We'll be ignoring anti-dependencies on non-allocatable registers,
/// because they may not be safe to break.
const BitVector AllocatableSet;
public:
SchedulePostRATDList(MachineBasicBlock *mbb, const TargetMachine &tm,
SchedulePostRATDList(MachineFunction &MF,
const MachineLoopInfo &MLI,
const MachineDominatorTree &MDT)
: ScheduleDAGInstrs(mbb, tm, MLI, MDT), Topo(SUnits) {}
: ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
AllocatableSet(TRI->getAllocatableSet(MF)) {}
void Schedule();
@ -100,13 +107,13 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
SchedulePostRATDList Scheduler(Fn, MLI, MDT);
// Loop over all of the basic blocks
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB) {
SchedulePostRATDList Scheduler(MBB, Fn.getTarget(), MLI, MDT);
Scheduler.Run();
Scheduler.Run(0, MBB);
Scheduler.EmitSchedule();
}
@ -195,10 +202,6 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
DOUT << "Critical path has total latency "
<< (Max ? Max->getDepth() + Max->Latency : 0) << "\n";
// We'll be ignoring anti-dependencies on non-allocatable registers, because
// they may not be safe to break.
const BitVector AllocatableSet = TRI->getAllocatableSet(*MF);
// Track progress along the critical path through the SUnit graph as we walk
// the instructions.
SUnit *CriticalPathSU = Max;
@ -444,8 +447,8 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
// TODO: Instead of picking the first free register, consider which might
// be the best.
if (AntiDepReg != 0) {
for (TargetRegisterClass::iterator R = RC->allocation_order_begin(*MF),
RE = RC->allocation_order_end(*MF); R != RE; ++R) {
for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF),
RE = RC->allocation_order_end(MF); R != RE; ++R) {
unsigned NewReg = *R;
// Don't replace a register with itself.
if (NewReg == AntiDepReg) continue;

22
lib/CodeGen/ScheduleDAG.cpp
View File

@ -21,14 +21,13 @@
#include <climits>
using namespace llvm;
ScheduleDAG::ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm)
: DAG(dag), BB(bb), TM(tm), MRI(BB->getParent()->getRegInfo()) {
TII = TM.getInstrInfo();
MF = BB->getParent();
TRI = TM.getRegisterInfo();
TLI = TM.getTargetLowering();
ConstPool = MF->getConstantPool();
ScheduleDAG::ScheduleDAG(MachineFunction &mf)
: DAG(0), BB(0), TM(mf.getTarget()),
TII(TM.getInstrInfo()),
TRI(TM.getRegisterInfo()),
TLI(TM.getTargetLowering()),
MF(mf), MRI(mf.getRegInfo()),
ConstPool(MF.getConstantPool()) {
}
ScheduleDAG::~ScheduleDAG() {}
@ -46,7 +45,12 @@ void ScheduleDAG::dumpSchedule() const {
/// Run - perform scheduling.
///
void ScheduleDAG::Run() {
void ScheduleDAG::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
SUnits.clear();
Sequence.clear();
DAG = dag;
BB = bb;
Schedule();
DOUT << "*** Final schedule ***\n";

2
lib/CodeGen/ScheduleDAGEmit.cpp
View File

@ -29,7 +29,7 @@
using namespace llvm;
void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
MI->addMemOperand(*MF, MO);
MI->addMemOperand(MF, MO);
}
void ScheduleDAG::EmitNoop() {

39
lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@ -52,16 +52,18 @@ namespace {
LE = Header->livein_end(); LI != LE; ++LI)
LoopLiveIns.insert(*LI);
VisitRegion(MDT.getNode(Header), Loop, LoopLiveIns);
const MachineDomTreeNode *Node = MDT.getNode(Header);
const MachineBasicBlock *MBB = Node->getBlock();
assert(Loop->contains(MBB) &&
"Loop does not contain header!");
VisitRegion(Node, MBB, Loop, LoopLiveIns);
}
private:
void VisitRegion(const MachineDomTreeNode *Node,
const MachineBasicBlock *MBB,
const MachineLoop *Loop,
const SmallSet<unsigned, 8> &LoopLiveIns) {
MachineBasicBlock *MBB = Node->getBlock();
if (!Loop->contains(MBB)) return;
unsigned Count = 0;
for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
I != E; ++I, ++Count) {
@ -77,33 +79,28 @@ namespace {
}
const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
for (unsigned I = 0, E = Children.size(); I != E; ++I)
VisitRegion(Children[I], Loop, LoopLiveIns);
for (std::vector<MachineDomTreeNode*>::const_iterator I =
Children.begin(), E = Children.end(); I != E; ++I) {
const MachineDomTreeNode *ChildNode = *I;
MachineBasicBlock *ChildBlock = ChildNode->getBlock();
if (Loop->contains(ChildBlock))
VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
}
}
};
}
ScheduleDAGInstrs::ScheduleDAGInstrs(MachineBasicBlock *bb,
const TargetMachine &tm,
ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo &mli,
const MachineDominatorTree &mdt)
: ScheduleDAG(0, bb, tm), MLI(mli), MDT(mdt) {}
: ScheduleDAG(mf), MLI(mli), MDT(mdt) {}
void ScheduleDAGInstrs::BuildSchedGraph() {
SUnits.clear();
SUnits.reserve(BB->size());
// We build scheduling units by walking a block's instruction list from bottom
// to top.
// Remember where defs and uses of each physical register are as we procede.
std::vector<SUnit *> Defs[TargetRegisterInfo::FirstVirtualRegister] = {};
std::vector<SUnit *> Uses[TargetRegisterInfo::FirstVirtualRegister] = {};
// Remember where unknown loads are after the most recent unknown store
// as we procede.
std::vector<SUnit *> PendingLoads;
// Remember where a generic side-effecting instruction is as we procede. If
// ChainMMO is null, this is assumed to have arbitrary side-effects. If
// ChainMMO is non-null, then Chain makes only a single memory reference.
@ -378,6 +375,12 @@ void ScheduleDAGInstrs::BuildSchedGraph() {
if (TID.isTerminator() || MI->isLabel())
Terminator = SU;
}
for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) {
Defs[i].clear();
Uses[i].clear();
}
PendingLoads.clear();
}
void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {

6
lib/CodeGen/ScheduleDAGPrinter.cpp
View File

@ -34,7 +34,7 @@ namespace llvm {
template<>
struct DOTGraphTraits<ScheduleDAG*> : public DefaultDOTGraphTraits {
static std::string getGraphName(const ScheduleDAG *G) {
return G->MF->getFunction()->getName();
return G->MF.getFunction()->getName();
}
static bool renderGraphFromBottomUp() {
@ -83,8 +83,8 @@ std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU,
void ScheduleDAG::viewGraph() {
// This code is only for debugging!
#ifndef NDEBUG
ViewGraph(this, "dag." + MF->getFunction()->getName(),
"Scheduling-Units Graph for " + MF->getFunction()->getName() + ':' +
ViewGraph(this, "dag." + MF.getFunction()->getName(),
"Scheduling-Units Graph for " + MF.getFunction()->getName() + ':' +
BB->getBasicBlock()->getName());
#else
cerr << "ScheduleDAG::viewGraph is only available in debug builds on "

4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -49,7 +49,7 @@ namespace {
class VISIBILITY_HIDDEN DAGCombiner {
SelectionDAG &DAG;
TargetLowering &TLI;
const TargetLowering &TLI;
CombineLevel Level;
bool LegalOperations;
bool LegalTypes;
@ -2836,7 +2836,7 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) {
static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
unsigned ExtOpc,
SmallVector<SDNode*, 4> &ExtendNodes,
TargetLowering &TLI) {
const TargetLowering &TLI) {
bool HasCopyToRegUses = false;
bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
for (SDNode::use_iterator UI = N0.getNode()->use_begin(),

14
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
View File

@ -14,9 +14,9 @@
#define DEBUG_TYPE "pre-RA-sched"
#include "llvm/CodeGen/ScheduleDAGSDNodes.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
@ -71,9 +71,8 @@ private:
std::vector<unsigned> LiveRegCycles;
public:
ScheduleDAGFast(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm)
: ScheduleDAGSDNodes(dag, bb, tm) {}
ScheduleDAGFast(MachineFunction &mf)
: ScheduleDAGSDNodes(mf) {}
void Schedule();
@ -619,9 +618,6 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
// Public Constructor Functions
//===----------------------------------------------------------------------===//
llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB, bool) {
return new ScheduleDAGFast(DAG, BB, *TM);
llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
return new ScheduleDAGFast(*IS->MF);
}

12
lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
View File

@ -25,7 +25,6 @@
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
@ -62,11 +61,10 @@ private:
HazardRecognizer *HazardRec;
public:
ScheduleDAGList(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm,
ScheduleDAGList(MachineFunction &mf,
SchedulingPriorityQueue *availqueue,
HazardRecognizer *HR)
: ScheduleDAGSDNodes(dag, bb, tm),
: ScheduleDAGSDNodes(mf),
AvailableQueue(availqueue), HazardRec(HR) {
}
@ -268,10 +266,8 @@ void ScheduleDAGList::ListScheduleTopDown() {
/// new hazard recognizer. This scheduler takes ownership of the hazard
/// recognizer and deletes it when done.
ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB, bool Fast) {
return new ScheduleDAGList(DAG, BB, *TM,
bool Fast) {
return new ScheduleDAGList(*IS->MF,
new LatencyPriorityQueue(),
IS->CreateTargetHazardRecognizer());
}

28
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -18,6 +18,7 @@
#define DEBUG_TYPE "pre-RA-sched"
#include "llvm/CodeGen/ScheduleDAGSDNodes.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
@ -72,10 +73,10 @@ private:
ScheduleDAGTopologicalSort Topo;
public:
ScheduleDAGRRList(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm, bool isbottomup,
ScheduleDAGRRList(MachineFunction &mf,
bool isbottomup,
SchedulingPriorityQueue *availqueue)
: ScheduleDAGSDNodes(dag, bb, tm), isBottomUp(isbottomup),
: ScheduleDAGSDNodes(mf), isBottomUp(isbottomup),
AvailableQueue(availqueue), Topo(SUnits) {
}
@ -1346,32 +1347,29 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
//===----------------------------------------------------------------------===//
llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool) {
const TargetInstrInfo *TII = TM->getInstrInfo();
const TargetRegisterInfo *TRI = TM->getRegisterInfo();
const TargetMachine &TM = IS->TM;
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI);
ScheduleDAGRRList *SD =
new ScheduleDAGRRList(DAG, BB, *TM, true, PQ);
new ScheduleDAGRRList(*IS->MF, true, PQ);
PQ->setScheduleDAG(SD);
return SD;
}
llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool) {
const TargetInstrInfo *TII = TM->getInstrInfo();
const TargetRegisterInfo *TRI = TM->getRegisterInfo();
const TargetMachine &TM = IS->TM;
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
TDRegReductionPriorityQueue *PQ = new TDRegReductionPriorityQueue(TII, TRI);
ScheduleDAGRRList *SD = new ScheduleDAGRRList(DAG, BB, *TM, false, PQ);
ScheduleDAGRRList *SD =
new ScheduleDAGRRList(*IS->MF, false, PQ);
PQ->setScheduleDAG(SD);
return SD;
}

5
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
View File

@ -22,9 +22,8 @@
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
ScheduleDAGSDNodes::ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm)
: ScheduleDAG(dag, bb, tm) {
ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
: ScheduleDAG(mf) {
}
SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {

8
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
View File

@ -381,7 +381,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
// Create the extract_subreg machine instruction.
MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
MachineInstr *MI = BuildMI(MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
// Figure out the register class to create for the destreg.
unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
@ -427,7 +427,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
}
// Create the insert_subreg or subreg_to_reg machine instruction.
MachineInstr *MI = BuildMI(*MF, TII->get(Opc));
MachineInstr *MI = BuildMI(MF, TII->get(Opc));
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
// If creating a subreg_to_reg, then the first input operand
@ -484,7 +484,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone,
#endif
// Create the new machine instruction.
MachineInstr *MI = BuildMI(*MF, II);
MachineInstr *MI = BuildMI(MF, II);
// Add result register values for things that are defined by this
// instruction.
@ -568,7 +568,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone,
--NumOps; // Ignore the flag operand.
// Create the inline asm machine instruction.
MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::INLINEASM));
MachineInstr *MI = BuildMI(MF, TII->get(TargetInstrInfo::INLINEASM));
// Add the asm string as an external symbol operand.
const char *AsmStr =

46
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -137,19 +137,16 @@ namespace llvm {
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast) {
const TargetLowering &TLI = IS->getTargetLowering();
if (Fast)
return createFastDAGScheduler(IS, DAG, TM, BB, Fast);
return createFastDAGScheduler(IS, Fast);
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
return createTDListDAGScheduler(IS, DAG, TM, BB, Fast);
return createTDListDAGScheduler(IS, Fast);
assert(TLI.getSchedulingPreference() ==
TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
return createBURRListDAGScheduler(IS, DAG, TM, BB, Fast);
return createBURRListDAGScheduler(IS, Fast);
}
}
@ -266,8 +263,8 @@ static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
// SelectionDAGISel code
//===----------------------------------------------------------------------===//
SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) :
FunctionPass(&ID), TLI(tli),
SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
FuncInfo(new FunctionLoweringInfo(TLI)),
CurDAG(new SelectionDAG(TLI, *FuncInfo)),
SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)),
@ -304,22 +301,21 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
AA = &getAnalysis<AliasAnalysis>();
TargetMachine &TM = TLI.getTargetMachine();
MachineFunction &MF = MachineFunction::construct(&Fn, TM);
const MachineRegisterInfo &MRI = MF.getRegInfo();
MF = &MachineFunction::construct(&Fn, TM);
const TargetInstrInfo &TII = *TM.getInstrInfo();
const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
if (MF.getFunction()->hasGC())
GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction());
if (MF->getFunction()->hasGC())
GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF->getFunction());
else
GFI = 0;
RegInfo = &MF.getRegInfo();
RegInfo = &MF->getRegInfo();
DOUT << "\n\n\n=== " << Fn.getName() << "\n";
FuncInfo->set(Fn, MF, EnableFastISel);
FuncInfo->set(Fn, *MF, EnableFastISel);
MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>();
DwarfWriter *DW = getAnalysisToUpdate<DwarfWriter>();
CurDAG->init(MF, MMI, DW);
CurDAG->init(*MF, MMI, DW);
SDL->init(GFI, *AA);
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
@ -327,17 +323,17 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
// Mark landing pad.
FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
SelectAllBasicBlocks(Fn, MF, MMI, DW, TII);
SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII);
// If the first basic block in the function has live ins that need to be
// copied into vregs, emit the copies into the top of the block before
// emitting the code for the block.
EmitLiveInCopies(MF.begin(), MRI, TRI, TII);
EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
// Add function live-ins to entry block live-in set.
for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
E = RegInfo->livein_end(); I != E; ++I)
MF.begin()->addLiveIn(I->first);
MF->begin()->addLiveIn(I->first);
#ifndef NDEBUG
assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
@ -365,7 +361,7 @@ static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
/// whether object offset >= 0.
static bool
IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
IsFixedFrameObjectWithPosOffset(MachineFrameInfo *MFI, SDValue Op) {
if (!isa<FrameIndexSDNode>(Op)) return false;
FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
@ -380,7 +376,7 @@ IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
/// virtual registers would be overwritten by direct lowering.
static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
MachineFrameInfo * MFI) {
MachineFrameInfo *MFI) {
RegisterSDNode * OpReg = NULL;
if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
(Op.getOpcode()== ISD::CopyFromReg &&
@ -694,14 +690,15 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
DEBUG(BB->dump());
}
void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
MachineFunction &MF,
MachineModuleInfo *MMI,
DwarfWriter *DW,
const TargetInstrInfo &TII) {
// Initialize the Fast-ISel state, if needed.
FastISel *FastIS = 0;
if (EnableFastISel)
FastIS = TLI.createFastISel(*FuncInfo->MF, MMI, DW,
FastIS = TLI.createFastISel(MF, MMI, DW,
FuncInfo->ValueMap,
FuncInfo->MBBMap,
FuncInfo->StaticAllocaMap
@ -1075,9 +1072,8 @@ ScheduleDAG *SelectionDAGISel::Schedule() {
RegisterScheduler::setDefault(Ctor);
}
TargetMachine &TM = getTargetLowering().getTargetMachine();
ScheduleDAG *Scheduler = Ctor(this, CurDAG, &TM, BB, Fast);
Scheduler->Run();
ScheduleDAG *Scheduler = Ctor(this, Fast);
Scheduler->Run(CurDAG, BB);
return Scheduler;
}

2
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -46,7 +46,7 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
public:
explicit ARMDAGToDAGISel(ARMTargetMachine &tm)
: SelectionDAGISel(*tm.getTargetLowering()), TM(tm),
: SelectionDAGISel(tm), TM(tm),
Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
}

2
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -143,7 +143,7 @@ namespace {
public:
explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
: SelectionDAGISel(*TM.getTargetLowering())
: SelectionDAGISel(TM)
{}
/// getI64Imm - Return a target constant with the specified value, of type

2
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -227,7 +227,7 @@ class SPUDAGToDAGISel :
public:
explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
SelectionDAGISel(*tm.getTargetLowering()),
SelectionDAGISel(tm),
TM(tm),
SPUtli(*tm.getTargetLowering())
{}

2
lib/Target/IA64/IA64ISelDAGToDAG.cpp
View File

@ -38,7 +38,7 @@ namespace {
unsigned GlobalBaseReg;
public:
explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
: SelectionDAGISel(*TM.getTargetLowering()) {}
: SelectionDAGISel(TM) {}
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary

2
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -55,7 +55,7 @@ class VISIBILITY_HIDDEN MipsDAGToDAGISel : public SelectionDAGISel {
public:
explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
SelectionDAGISel(*tm.getTargetLowering()),
SelectionDAGISel(tm),
TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
virtual void InstructionSelect();

2
lib/Target/PIC16/PIC16ISelDAGToDAG.h
View File

@ -35,7 +35,7 @@ class VISIBILITY_HIDDEN PIC16DAGToDAGISel : public SelectionDAGISel {
public:
explicit PIC16DAGToDAGISel(PIC16TargetMachine &tm) :
SelectionDAGISel(PIC16Lowering),
SelectionDAGISel(tm),
TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
// Pass Name

2
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -44,7 +44,7 @@ namespace {
unsigned GlobalBaseReg;
public:
explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
: SelectionDAGISel(*tm.getTargetLowering()), TM(tm),
: SelectionDAGISel(tm), TM(tm),
PPCLowering(*TM.getTargetLowering()),
PPCSubTarget(*TM.getSubtargetImpl()) {}

2
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -34,7 +34,7 @@ class SparcDAGToDAGISel : public SelectionDAGISel {
const SparcSubtarget &Subtarget;
public:
explicit SparcDAGToDAGISel(SparcTargetMachine &TM)
: SelectionDAGISel(*TM.getTargetLowering()),
: SelectionDAGISel(TM),
Subtarget(TM.getSubtarget<SparcSubtarget>()) {
}

2
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -126,7 +126,7 @@ namespace {
public:
X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
: SelectionDAGISel(*tm.getTargetLowering(), fast),
: SelectionDAGISel(tm, fast),
TM(tm), X86Lowering(*TM.getTargetLowering()),
Subtarget(&TM.getSubtarget<X86Subtarget>()),
OptForSize(false) {}

2
lib/Target/XCore/XCoreISelDAGToDAG.cpp
View File

@ -42,7 +42,7 @@ namespace {
public:
XCoreDAGToDAGISel(XCoreTargetMachine &TM)
: SelectionDAGISel(*TM.getTargetLowering()),
: SelectionDAGISel(TM),
Lowering(*TM.getTargetLowering()),
Subtarget(*TM.getSubtargetImpl()) { }