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[ARM] Rename NEONModImm to VMOVModImm. NFC

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Rename NEONModImm to VMOVModImm as it is used in both NEON and MVE.

llvm-svn: 366790
This commit is contained in:
David Green 2019-07-23 09:19:24 +00:00
parent 9bc116566e
commit 6fde6fb1ae
8 changed files with 46 additions and 46 deletions
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32
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -5146,7 +5146,7 @@ SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
if (UseNEON) { if (UseNEON) {
// Use VBSL to copy the sign bit. // Use VBSL to copy the sign bit.
unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80); unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
DAG.getTargetConstant(EncodedVal, dl, MVT::i32)); DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
@ -5169,7 +5169,7 @@ SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
dl, MVT::i32); dl, MVT::i32);
AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
@ -6033,13 +6033,13 @@ static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) {
CCR, Chain.getValue(1)); CCR, Chain.getValue(1));
} }
/// isNEONModifiedImm - Check if the specified splat value corresponds to a /// isVMOVModifiedImm - Check if the specified splat value corresponds to a
/// valid vector constant for a NEON or MVE instruction with a "modified immediate" /// valid vector constant for a NEON or MVE instruction with a "modified
/// operand (e.g., VMOV). If so, return the encoded value. /// immediate" operand (e.g., VMOV). If so, return the encoded value.
static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, static SDValue isVMOVModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
unsigned SplatBitSize, SelectionDAG &DAG, unsigned SplatBitSize, SelectionDAG &DAG,
const SDLoc &dl, EVT &VT, bool is128Bits, const SDLoc &dl, EVT &VT, bool is128Bits,
NEONModImmType type) { VMOVModImmType type) {
unsigned OpCmode, Imm; unsigned OpCmode, Imm;
// SplatBitSize is set to the smallest size that splats the vector, so a // SplatBitSize is set to the smallest size that splats the vector, so a
@ -6169,10 +6169,10 @@ static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
} }
default: default:
llvm_unreachable("unexpected size for isNEONModifiedImm"); llvm_unreachable("unexpected size for isVMOVModifiedImm");
} }
unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); unsigned EncodedVal = ARM_AM::createVMOVModImm(OpCmode, Imm);
return DAG.getTargetConstant(EncodedVal, dl, MVT::i32); return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
} }
@ -6252,7 +6252,7 @@ SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
return SDValue(); return SDValue();
// Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too). // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), SDValue NewVal = isVMOVModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
VMovVT, false, VMOVModImm); VMovVT, false, VMOVModImm);
if (NewVal != SDValue()) { if (NewVal != SDValue()) {
SDLoc DL(Op); SDLoc DL(Op);
@ -6269,7 +6269,7 @@ SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
} }
// Finally, try a VMVN.i32 // Finally, try a VMVN.i32
NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT, NewVal = isVMOVModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
false, VMVNModImm); false, VMVNModImm);
if (NewVal != SDValue()) { if (NewVal != SDValue()) {
SDLoc DL(Op); SDLoc DL(Op);
@ -6694,7 +6694,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
(ST->hasMVEIntegerOps() && SplatBitSize <= 32)) { (ST->hasMVEIntegerOps() && SplatBitSize <= 32)) {
// Check if an immediate VMOV works. // Check if an immediate VMOV works.
EVT VmovVT; EVT VmovVT;
SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), SDValue Val = isVMOVModifiedImm(SplatBits.getZExtValue(),
SplatUndef.getZExtValue(), SplatBitSize, SplatUndef.getZExtValue(), SplatBitSize,
DAG, dl, VmovVT, VT.is128BitVector(), DAG, dl, VmovVT, VT.is128BitVector(),
VMOVModImm); VMOVModImm);
@ -6706,7 +6706,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
// Try an immediate VMVN. // Try an immediate VMVN.
uint64_t NegatedImm = (~SplatBits).getZExtValue(); uint64_t NegatedImm = (~SplatBits).getZExtValue();
Val = isNEONModifiedImm( Val = isVMOVModifiedImm(
NegatedImm, SplatUndef.getZExtValue(), SplatBitSize, NegatedImm, SplatUndef.getZExtValue(), SplatBitSize,
DAG, dl, VmovVT, VT.is128BitVector(), DAG, dl, VmovVT, VT.is128BitVector(),
ST->hasMVEIntegerOps() ? MVEVMVNModImm : VMVNModImm); ST->hasMVEIntegerOps() ? MVEVMVNModImm : VMVNModImm);
@ -11259,7 +11259,7 @@ static SDValue PerformANDCombine(SDNode *N,
BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
if (SplatBitSize <= 64) { if (SplatBitSize <= 64) {
EVT VbicVT; EVT VbicVT;
SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), SDValue Val = isVMOVModifiedImm((~SplatBits).getZExtValue(),
SplatUndef.getZExtValue(), SplatBitSize, SplatUndef.getZExtValue(), SplatBitSize,
DAG, dl, VbicVT, VT.is128BitVector(), DAG, dl, VbicVT, VT.is128BitVector(),
OtherModImm); OtherModImm);
@ -11495,7 +11495,7 @@ static SDValue PerformORCombine(SDNode *N,
BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
if (SplatBitSize <= 64) { if (SplatBitSize <= 64) {
EVT VorrVT; EVT VorrVT;
SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), SDValue Val = isVMOVModifiedImm(SplatBits.getZExtValue(),
SplatUndef.getZExtValue(), SplatBitSize, SplatUndef.getZExtValue(), SplatBitSize,
DAG, dl, VorrVT, VT.is128BitVector(), DAG, dl, VorrVT, VT.is128BitVector(),
OtherModImm); OtherModImm);
@ -12338,7 +12338,7 @@ static SDValue PerformVDUPLANECombine(SDNode *N,
// The canonical VMOV for a zero vector uses a 32-bit element size. // The canonical VMOV for a zero vector uses a 32-bit element size.
unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
unsigned EltBits; unsigned EltBits;
if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0) if (ARM_AM::decodeVMOVModImm(Imm, EltBits) == 0)
EltSize = 8; EltSize = 8;
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
if (EltSize > VT.getScalarSizeInBits()) if (EltSize > VT.getScalarSizeInBits())

2
lib/Target/ARM/ARMISelLowering.h
View File

@ -838,7 +838,7 @@ class VectorType;
void setAllExpand(MVT VT); void setAllExpand(MVT VT);
}; };
enum NEONModImmType { enum VMOVModImmType {
VMOVModImm, VMOVModImm,
VMVNModImm, VMVNModImm,
MVEVMVNModImm, MVEVMVNModImm,

2
lib/Target/ARM/ARMInstrFormats.td
View File

@ -2282,7 +2282,7 @@ class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
let Inst{24} = SIMM{7}; let Inst{24} = SIMM{7};
let Inst{18-16} = SIMM{6-4}; let Inst{18-16} = SIMM{6-4};
let Inst{3-0} = SIMM{3-0}; let Inst{3-0} = SIMM{3-0};
let DecoderMethod = "DecodeNEONModImmInstruction"; let DecoderMethod = "DecodeVMOVModImmInstruction";
} }
// NEON 2 vector register format. // NEON 2 vector register format.

22
lib/Target/ARM/ARMInstrNEON.td
View File

@ -15,22 +15,22 @@
// NEON-specific Operands. // NEON-specific Operands.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def nModImm : Operand<i32> { def nModImm : Operand<i32> {
let PrintMethod = "printNEONModImmOperand"; let PrintMethod = "printVMOVModImmOperand";
} }
def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; } def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
def nImmSplatI8 : Operand<i32> { def nImmSplatI8 : Operand<i32> {
let PrintMethod = "printNEONModImmOperand"; let PrintMethod = "printVMOVModImmOperand";
let ParserMatchClass = nImmSplatI8AsmOperand; let ParserMatchClass = nImmSplatI8AsmOperand;
} }
def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; } def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
def nImmSplatI16 : Operand<i32> { def nImmSplatI16 : Operand<i32> {
let PrintMethod = "printNEONModImmOperand"; let PrintMethod = "printVMOVModImmOperand";
let ParserMatchClass = nImmSplatI16AsmOperand; let ParserMatchClass = nImmSplatI16AsmOperand;
} }
def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; } def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
def nImmSplatI32 : Operand<i32> { def nImmSplatI32 : Operand<i32> {
let PrintMethod = "printNEONModImmOperand"; let PrintMethod = "printVMOVModImmOperand";
let ParserMatchClass = nImmSplatI32AsmOperand; let ParserMatchClass = nImmSplatI32AsmOperand;
} }
def nImmSplatNotI16AsmOperand : AsmOperandClass { let Name = "NEONi16splatNot"; } def nImmSplatNotI16AsmOperand : AsmOperandClass { let Name = "NEONi16splatNot"; }
@ -43,7 +43,7 @@ def nImmSplatNotI32 : Operand<i32> {
} }
def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; } def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
def nImmVMOVI32 : Operand<i32> { def nImmVMOVI32 : Operand<i32> {
let PrintMethod = "printNEONModImmOperand"; let PrintMethod = "printVMOVModImmOperand";
let ParserMatchClass = nImmVMOVI32AsmOperand; let ParserMatchClass = nImmVMOVI32AsmOperand;
} }
@ -62,18 +62,18 @@ class nImmVINVIAsmOperandReplicate<ValueType From, ValueType To>
} }
class nImmVMOVIReplicate<ValueType From, ValueType To> : Operand<i32> { class nImmVMOVIReplicate<ValueType From, ValueType To> : Operand<i32> {
let PrintMethod = "printNEONModImmOperand"; let PrintMethod = "printVMOVModImmOperand";
let ParserMatchClass = nImmVMOVIAsmOperandReplicate<From, To>; let ParserMatchClass = nImmVMOVIAsmOperandReplicate<From, To>;
} }
class nImmVINVIReplicate<ValueType From, ValueType To> : Operand<i32> { class nImmVINVIReplicate<ValueType From, ValueType To> : Operand<i32> {
let PrintMethod = "printNEONModImmOperand"; let PrintMethod = "printVMOVModImmOperand";
let ParserMatchClass = nImmVINVIAsmOperandReplicate<From, To>; let ParserMatchClass = nImmVINVIAsmOperandReplicate<From, To>;
} }
def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; } def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
def nImmVMOVI32Neg : Operand<i32> { def nImmVMOVI32Neg : Operand<i32> {
let PrintMethod = "printNEONModImmOperand"; let PrintMethod = "printVMOVModImmOperand";
let ParserMatchClass = nImmVMOVI32NegAsmOperand; let ParserMatchClass = nImmVMOVI32NegAsmOperand;
} }
def nImmVMOVF32 : Operand<i32> { def nImmVMOVF32 : Operand<i32> {
@ -82,7 +82,7 @@ def nImmVMOVF32 : Operand<i32> {
} }
def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; } def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
def nImmSplatI64 : Operand<i32> { def nImmSplatI64 : Operand<i32> {
let PrintMethod = "printNEONModImmOperand"; let PrintMethod = "printVMOVModImmOperand";
let ParserMatchClass = nImmSplatI64AsmOperand; let ParserMatchClass = nImmSplatI64AsmOperand;
} }
@ -559,14 +559,14 @@ def NEONvtbl2 : SDNode<"ARMISD::VTBL2", SDTARMVTBL2>;
def NEONimmAllZerosV: PatLeaf<(ARMvmovImm (i32 timm)), [{ def NEONimmAllZerosV: PatLeaf<(ARMvmovImm (i32 timm)), [{
ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0)); ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
unsigned EltBits = 0; unsigned EltBits = 0;
uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits); uint64_t EltVal = ARM_AM::decodeVMOVModImm(ConstVal->getZExtValue(), EltBits);
return (EltBits == 32 && EltVal == 0); return (EltBits == 32 && EltVal == 0);
}]>; }]>;
def NEONimmAllOnesV: PatLeaf<(ARMvmovImm (i32 timm)), [{ def NEONimmAllOnesV: PatLeaf<(ARMvmovImm (i32 timm)), [{
ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0)); ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
unsigned EltBits = 0; unsigned EltBits = 0;
uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits); uint64_t EltVal = ARM_AM::decodeVMOVModImm(ConstVal->getZExtValue(), EltBits);
return (EltBits == 8 && EltVal == 0xff); return (EltBits == 8 && EltVal == 0xff);
}]>; }]>;

8
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -314,7 +314,7 @@ static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
@ -3445,7 +3445,7 @@ static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
} }
static DecodeStatus static DecodeStatus
DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
@ -5679,7 +5679,7 @@ static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
} }
} }
} }
return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
} }
if (!(imm & 0x20)) return MCDisassembler::Fail; if (!(imm & 0x20)) return MCDisassembler::Fail;
@ -5738,7 +5738,7 @@ static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
} }
} }
} }
return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
} }
if (!(imm & 0x20)) return MCDisassembler::Fail; if (!(imm & 0x20)) return MCDisassembler::Fail;

20
lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
View File

@ -518,10 +518,10 @@ namespace ARM_AM {
// Valid alignments depend on the specific instruction. // Valid alignments depend on the specific instruction.
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// NEON Modified Immediates // NEON/MVE Modified Immediates
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// //
// Several NEON instructions (e.g., VMOV) take a "modified immediate" // Several NEON and MVE instructions (e.g., VMOV) take a "modified immediate"
// vector operand, where a small immediate encoded in the instruction // vector operand, where a small immediate encoded in the instruction
// specifies a full NEON vector value. These modified immediates are // specifies a full NEON vector value. These modified immediates are
// represented here as encoded integers. The low 8 bits hold the immediate // represented here as encoded integers. The low 8 bits hold the immediate
@ -529,20 +529,20 @@ namespace ARM_AM {
// the "Cmode" field of the instruction. The interfaces below treat the // the "Cmode" field of the instruction. The interfaces below treat the
// Op and Cmode values as a single 5-bit value. // Op and Cmode values as a single 5-bit value.
inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) { inline unsigned createVMOVModImm(unsigned OpCmode, unsigned Val) {
return (OpCmode << 8) | Val; return (OpCmode << 8) | Val;
} }
inline unsigned getNEONModImmOpCmode(unsigned ModImm) { inline unsigned getVMOVModImmOpCmode(unsigned ModImm) {
return (ModImm >> 8) & 0x1f; return (ModImm >> 8) & 0x1f;
} }
inline unsigned getNEONModImmVal(unsigned ModImm) { return ModImm & 0xff; } inline unsigned getVMOVModImmVal(unsigned ModImm) { return ModImm & 0xff; }
/// decodeNEONModImm - Decode a NEON modified immediate value into the /// decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the
/// element value and the element size in bits. (If the element size is /// element value and the element size in bits. (If the element size is
/// smaller than the vector, it is splatted into all the elements.) /// smaller than the vector, it is splatted into all the elements.)
inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) { inline uint64_t decodeVMOVModImm(unsigned ModImm, unsigned &EltBits) {
unsigned OpCmode = getNEONModImmOpCmode(ModImm); unsigned OpCmode = getVMOVModImmOpCmode(ModImm);
unsigned Imm8 = getNEONModImmVal(ModImm); unsigned Imm8 = getVMOVModImmVal(ModImm);
uint64_t Val = 0; uint64_t Val = 0;
if (OpCmode == 0xe) { if (OpCmode == 0xe) {
@ -572,7 +572,7 @@ namespace ARM_AM {
} }
EltBits = 64; EltBits = 64;
} else { } else {
llvm_unreachable("Unsupported NEON immediate"); llvm_unreachable("Unsupported VMOV immediate");
} }
return Val; return Val;
} }

4
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
View File

@ -1334,12 +1334,12 @@ void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
<< markup(">"); << markup(">");
} }
void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printVMOVModImmOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
unsigned EncodedImm = MI->getOperand(OpNum).getImm(); unsigned EncodedImm = MI->getOperand(OpNum).getImm();
unsigned EltBits; unsigned EltBits;
uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits); uint64_t Val = ARM_AM::decodeVMOVModImm(EncodedImm, EltBits);
O << markup("<imm:") << "#0x"; O << markup("<imm:") << "#0x";
O.write_hex(Val); O.write_hex(Val);
O << markup(">"); O << markup(">");

2
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
View File

@ -191,7 +191,7 @@ public:
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
void printFPImmOperand(const MCInst *MI, unsigned OpNum, void printFPImmOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, void printVMOVModImmOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);