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https://github.com/RPCS3/llvm-mirror.git
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[ARM] Rename NEONModImm to VMOVModImm. NFC
Rename NEONModImm to VMOVModImm as it is used in both NEON and MVE. llvm-svn: 366790
This commit is contained in:
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@ -5146,7 +5146,7 @@ SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
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if (UseNEON) {
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// Use VBSL to copy the sign bit.
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unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
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unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
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SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
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DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
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EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
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@ -5169,7 +5169,7 @@ SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
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Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
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Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
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SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
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SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
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dl, MVT::i32);
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AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
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SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
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@ -6033,13 +6033,13 @@ static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) {
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CCR, Chain.getValue(1));
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}
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/// isNEONModifiedImm - Check if the specified splat value corresponds to a
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/// valid vector constant for a NEON or MVE instruction with a "modified immediate"
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/// operand (e.g., VMOV). If so, return the encoded value.
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static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
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/// isVMOVModifiedImm - Check if the specified splat value corresponds to a
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/// valid vector constant for a NEON or MVE instruction with a "modified
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/// immediate" operand (e.g., VMOV). If so, return the encoded value.
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static SDValue isVMOVModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
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unsigned SplatBitSize, SelectionDAG &DAG,
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const SDLoc &dl, EVT &VT, bool is128Bits,
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NEONModImmType type) {
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VMOVModImmType type) {
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unsigned OpCmode, Imm;
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// SplatBitSize is set to the smallest size that splats the vector, so a
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@ -6169,10 +6169,10 @@ static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
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}
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default:
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llvm_unreachable("unexpected size for isNEONModifiedImm");
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llvm_unreachable("unexpected size for isVMOVModifiedImm");
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}
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unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
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unsigned EncodedVal = ARM_AM::createVMOVModImm(OpCmode, Imm);
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return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
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}
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@ -6252,7 +6252,7 @@ SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
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return SDValue();
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// Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
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SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
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SDValue NewVal = isVMOVModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
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VMovVT, false, VMOVModImm);
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if (NewVal != SDValue()) {
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SDLoc DL(Op);
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@ -6269,7 +6269,7 @@ SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
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}
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// Finally, try a VMVN.i32
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NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
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NewVal = isVMOVModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
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false, VMVNModImm);
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if (NewVal != SDValue()) {
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SDLoc DL(Op);
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@ -6694,7 +6694,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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(ST->hasMVEIntegerOps() && SplatBitSize <= 32)) {
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// Check if an immediate VMOV works.
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EVT VmovVT;
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SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
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SDValue Val = isVMOVModifiedImm(SplatBits.getZExtValue(),
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SplatUndef.getZExtValue(), SplatBitSize,
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DAG, dl, VmovVT, VT.is128BitVector(),
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VMOVModImm);
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@ -6706,7 +6706,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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// Try an immediate VMVN.
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uint64_t NegatedImm = (~SplatBits).getZExtValue();
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Val = isNEONModifiedImm(
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Val = isVMOVModifiedImm(
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NegatedImm, SplatUndef.getZExtValue(), SplatBitSize,
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DAG, dl, VmovVT, VT.is128BitVector(),
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ST->hasMVEIntegerOps() ? MVEVMVNModImm : VMVNModImm);
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@ -11259,7 +11259,7 @@ static SDValue PerformANDCombine(SDNode *N,
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BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
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if (SplatBitSize <= 64) {
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EVT VbicVT;
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SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
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SDValue Val = isVMOVModifiedImm((~SplatBits).getZExtValue(),
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SplatUndef.getZExtValue(), SplatBitSize,
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DAG, dl, VbicVT, VT.is128BitVector(),
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OtherModImm);
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@ -11495,7 +11495,7 @@ static SDValue PerformORCombine(SDNode *N,
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BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
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if (SplatBitSize <= 64) {
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EVT VorrVT;
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SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
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SDValue Val = isVMOVModifiedImm(SplatBits.getZExtValue(),
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SplatUndef.getZExtValue(), SplatBitSize,
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DAG, dl, VorrVT, VT.is128BitVector(),
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OtherModImm);
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@ -12338,7 +12338,7 @@ static SDValue PerformVDUPLANECombine(SDNode *N,
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// The canonical VMOV for a zero vector uses a 32-bit element size.
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unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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unsigned EltBits;
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if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
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if (ARM_AM::decodeVMOVModImm(Imm, EltBits) == 0)
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EltSize = 8;
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EVT VT = N->getValueType(0);
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if (EltSize > VT.getScalarSizeInBits())
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@ -838,7 +838,7 @@ class VectorType;
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void setAllExpand(MVT VT);
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};
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enum NEONModImmType {
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enum VMOVModImmType {
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VMOVModImm,
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VMVNModImm,
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MVEVMVNModImm,
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@ -2282,7 +2282,7 @@ class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
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let Inst{24} = SIMM{7};
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let Inst{18-16} = SIMM{6-4};
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let Inst{3-0} = SIMM{3-0};
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let DecoderMethod = "DecodeNEONModImmInstruction";
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let DecoderMethod = "DecodeVMOVModImmInstruction";
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}
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// NEON 2 vector register format.
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@ -15,22 +15,22 @@
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// NEON-specific Operands.
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//===----------------------------------------------------------------------===//
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def nModImm : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let PrintMethod = "printVMOVModImmOperand";
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}
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def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
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def nImmSplatI8 : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let PrintMethod = "printVMOVModImmOperand";
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let ParserMatchClass = nImmSplatI8AsmOperand;
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}
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def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
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def nImmSplatI16 : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let PrintMethod = "printVMOVModImmOperand";
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let ParserMatchClass = nImmSplatI16AsmOperand;
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}
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def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
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def nImmSplatI32 : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let PrintMethod = "printVMOVModImmOperand";
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let ParserMatchClass = nImmSplatI32AsmOperand;
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}
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def nImmSplatNotI16AsmOperand : AsmOperandClass { let Name = "NEONi16splatNot"; }
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@ -43,7 +43,7 @@ def nImmSplatNotI32 : Operand<i32> {
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}
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def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
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def nImmVMOVI32 : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let PrintMethod = "printVMOVModImmOperand";
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let ParserMatchClass = nImmVMOVI32AsmOperand;
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}
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@ -62,18 +62,18 @@ class nImmVINVIAsmOperandReplicate<ValueType From, ValueType To>
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}
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class nImmVMOVIReplicate<ValueType From, ValueType To> : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let PrintMethod = "printVMOVModImmOperand";
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let ParserMatchClass = nImmVMOVIAsmOperandReplicate<From, To>;
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}
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class nImmVINVIReplicate<ValueType From, ValueType To> : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let PrintMethod = "printVMOVModImmOperand";
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let ParserMatchClass = nImmVINVIAsmOperandReplicate<From, To>;
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}
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def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
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def nImmVMOVI32Neg : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let PrintMethod = "printVMOVModImmOperand";
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let ParserMatchClass = nImmVMOVI32NegAsmOperand;
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}
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def nImmVMOVF32 : Operand<i32> {
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@ -82,7 +82,7 @@ def nImmVMOVF32 : Operand<i32> {
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}
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def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
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def nImmSplatI64 : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let PrintMethod = "printVMOVModImmOperand";
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let ParserMatchClass = nImmSplatI64AsmOperand;
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}
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@ -559,14 +559,14 @@ def NEONvtbl2 : SDNode<"ARMISD::VTBL2", SDTARMVTBL2>;
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def NEONimmAllZerosV: PatLeaf<(ARMvmovImm (i32 timm)), [{
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ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
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unsigned EltBits = 0;
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uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
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uint64_t EltVal = ARM_AM::decodeVMOVModImm(ConstVal->getZExtValue(), EltBits);
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return (EltBits == 32 && EltVal == 0);
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}]>;
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def NEONimmAllOnesV: PatLeaf<(ARMvmovImm (i32 timm)), [{
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ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
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unsigned EltBits = 0;
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uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
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uint64_t EltVal = ARM_AM::decodeVMOVModImm(ConstVal->getZExtValue(), EltBits);
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return (EltBits == 8 && EltVal == 0xff);
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}]>;
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@ -314,7 +314,7 @@ static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
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static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
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uint64_t Address, const void *Decoder);
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@ -3445,7 +3445,7 @@ static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
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}
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static DecodeStatus
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DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
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DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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@ -5679,7 +5679,7 @@ static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
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}
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}
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}
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return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
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return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
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}
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if (!(imm & 0x20)) return MCDisassembler::Fail;
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@ -5738,7 +5738,7 @@ static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
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}
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}
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}
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return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
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return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
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}
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if (!(imm & 0x20)) return MCDisassembler::Fail;
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@ -518,10 +518,10 @@ namespace ARM_AM {
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// Valid alignments depend on the specific instruction.
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//===--------------------------------------------------------------------===//
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// NEON Modified Immediates
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// NEON/MVE Modified Immediates
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//===--------------------------------------------------------------------===//
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//
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// Several NEON instructions (e.g., VMOV) take a "modified immediate"
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// Several NEON and MVE instructions (e.g., VMOV) take a "modified immediate"
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// vector operand, where a small immediate encoded in the instruction
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// specifies a full NEON vector value. These modified immediates are
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// represented here as encoded integers. The low 8 bits hold the immediate
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@ -529,20 +529,20 @@ namespace ARM_AM {
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// the "Cmode" field of the instruction. The interfaces below treat the
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// Op and Cmode values as a single 5-bit value.
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inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) {
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inline unsigned createVMOVModImm(unsigned OpCmode, unsigned Val) {
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return (OpCmode << 8) | Val;
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}
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inline unsigned getNEONModImmOpCmode(unsigned ModImm) {
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inline unsigned getVMOVModImmOpCmode(unsigned ModImm) {
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return (ModImm >> 8) & 0x1f;
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}
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inline unsigned getNEONModImmVal(unsigned ModImm) { return ModImm & 0xff; }
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inline unsigned getVMOVModImmVal(unsigned ModImm) { return ModImm & 0xff; }
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/// decodeNEONModImm - Decode a NEON modified immediate value into the
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/// decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the
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/// element value and the element size in bits. (If the element size is
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/// smaller than the vector, it is splatted into all the elements.)
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inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) {
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unsigned OpCmode = getNEONModImmOpCmode(ModImm);
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unsigned Imm8 = getNEONModImmVal(ModImm);
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inline uint64_t decodeVMOVModImm(unsigned ModImm, unsigned &EltBits) {
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unsigned OpCmode = getVMOVModImmOpCmode(ModImm);
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unsigned Imm8 = getVMOVModImmVal(ModImm);
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uint64_t Val = 0;
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if (OpCmode == 0xe) {
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@ -572,7 +572,7 @@ namespace ARM_AM {
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}
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EltBits = 64;
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} else {
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llvm_unreachable("Unsupported NEON immediate");
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llvm_unreachable("Unsupported VMOV immediate");
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}
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return Val;
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}
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@ -1334,12 +1334,12 @@ void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
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<< markup(">");
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}
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void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
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void ARMInstPrinter::printVMOVModImmOperand(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned EncodedImm = MI->getOperand(OpNum).getImm();
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unsigned EltBits;
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uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
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uint64_t Val = ARM_AM::decodeVMOVModImm(EncodedImm, EltBits);
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O << markup("<imm:") << "#0x";
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O.write_hex(Val);
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O << markup(">");
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@ -191,7 +191,7 @@ public:
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printFPImmOperand(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
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void printVMOVModImmOperand(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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